Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1995-08-21
2002-06-18
Jackson, Jerome (Department: 2503)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S207000, C257S211000, C257S758000, C257S776000, C438S180000
Reexamination Certificate
active
06407434
ABSTRACT:
FIELD OF THE INVENTION
This specification discloses a plurality of inventions relating generally to the art of microelectronic integrated circuits and electronic systems incorporating such circuits, and the disclosed subject matter may be specifically applied to microelectronic semiconductor integrated circuit structures and methods of designing and manufacturing semiconductor devices.
BACKGROUND OF THE DISCLOSURE
The fabrication of semiconductor devices has progressed significantly over the last four decades. Semiconductor chips incorporating over a million transistors are possible. However, the development of technologies such as interactive high-definition television, personal global communications systems, virtual reality applications, real-life graphics animation, and other scientific and industrial applications, will demand higher speed, more functionality, and further advances in very large scale integration technology. The demand for more functionality will require an increase in the number of transistors that need to be integrated on a chip. This will require shrinking the area required to fabricate interconnected transistors, or will require larger die sizes, or both. As the feature size decreases, and the area required to fabricate transistors decreases, the resulting increased density of devices will require an increasing number of interconnections within a chip, or interconnections between chips in a multi-chip design.
Transistors or gates typically make up a circuit cell. Each cell of an integrated circuit includes a plurality of points, sometimes referred to as pins or terminals, each of which must be connected to pins of other cells by an electrical interconnect wire network or net. Cells may comprise individual logic gates, or more preferably may each comprise a plurality of logic gates or transistors that are interconnected to form functional blocks. It is desirable to attempt to optimize a design so that the total wirelength and interconnect congestion are minimized.
As the number of transistors on a single chip becomes very large, gains made in reducing the feature size brought on by advances in fabrication technology may be offset by the increased area required for interconnection. As the number of interconnections increase, the amount of real estate on the semiconductor die occupied by interconnections could become relatively large unless steps are taken to improve conventional layout techniques.
It is desirable to achieve minimum area layouts for very large scale integration circuits, because minimum area layouts typically deliver optimum performance and provide the most economical implementation of a circuit. It is therefore desirable to have an architecture that will minimize the area occupied by the active part of the circuit. For example, an architecture that will tile well may provide advantages in minimizing the area occupied by the active part of the circuit. It is also desirable to have an architecture that will minimize the area occupied by the passive part of the circuit, i.e., the interconnection. This may be achieved by an architecture that provides better routing options. Ultimately, the theoretical lower limit on minimizing the area occupied by the interconnections is a zero-routing footprint chip.
In the early days of large scale integration, only a single layer of metal was available for routing, and polysilicon (polycrystalline silicon) and a single such metal layer were used to complete the interconnections. The first metal layer may be referred to as the “metal
1
” layer or “M
1
” layer. As semiconductor fabrication processes improved, a second metal layer was added. The second metal layer may be referred to as the “metal
2
” layer or “M
2
” layer. A rectangular approach to routing was used to determine the location of interconnections. Fabrication processes have now been developed which provide three or four metal layers. Fabrication processes which provide five or more metal layers are also being developed. Conductors can be formed in layers that are electrically insulated from the cells and extend over the cells, in what is sometimes referred to as over-the-cell routing. With three or four metal layers available for routing, it may be possible to approach a chip containing no area set aside exclusively for routing (i.e., a zero-routing footprint chip) if over-the-cell routing is utilized.
The performance of a chip depends on the maximum wire length of the interconnection metal used. For better performance, it is desirable to minimize the maximum wire length. As the feature size is made smaller, the delay per unit length of interconnection increases. According to one reference, a 7 micron NMOS technology may have a per unit resistance of 21 ohms per centimeter; and by comparison, a 0.35 micron CMOS technology may have a per unit resistance of 2440 ohms per centimeter. See N. Sherwani, S. Bhingarde & A. Panyam,
Routing in the Third Dimension
, at 8 (1995), the entirety of which is incorporated herein by reference.
The performance of a chip is bound by the time required for computation by the logic devices and the time required for the data communication. In the past, the time required for data communication was typically insignificant compared to the time required for computation, and could be neglected. In the past three decades, there has been a significant improvement in the average speed of computation time per gate. Now, the interconnection delays are on the order of gate delays and as a result, have become significant and can no longer be ignored. Interconnect delays are an increasing percentage of path delay.
When two points are interconnected by metal, a connection is formed which may be referred to as a wire. When two wires in the same metal layer run parallel to each other, parasitic capacitances may be significant and “crosstalk” may occur between signals on those wires. The metal
1
layer is typically separated from the metal
2
layer by a dielectric. When only two metal layers were used, a rectangular or rectilinear approach to routing provided metal
1
wires at 90 degrees relative to metal
2
wires, and this gave satisfactory results in many instances. However, a rectangular approach to routing when three metal layers are available has provided metal
3
wires parallel to metal
1
wires, and these metal layers are separated by layers of dielectric. This has resulted in unsatisfactory capacitance and “crosstalk” in many instances. With four metal layers, metal layers M
1
and M
3
may have parallel wires, and metal layers M
2
and M
4
may have parallel wires. Significant performance degradation may result. In the past, efforts to increase the number of metal layers in an attempt to approach a zero-routing footprint chip have resulted in offsetting performance degradation due to unsatisfactory capacitance and “crosstalk” from parallel wires located in different metal layers.
Microelectronic integrated circuits consist of a large number of electronic components that are fabricated by layering several different materials on a silicon base or wafer. The design of an integrated circuit transforms a circuit description into a geometric description which is known as a layout. A layout consists of a set of planar geometric shapes in several layers.
Typically, the layout is then checked to ensure that it meets all of the design requirements. The result is a set of design files in a particular unambiguous representation known as an intermediate form that describes the layout. The design files are then converted into pattern generator files that are used to produce patterns by an optical or electron beam pattern generator that are called masks.
During fabrication, these masks are used to pattern a silicon wafer using a sequence of photolithographic steps. This component formation requires very exacting details about geometric patterns and separation between them. These details are expressed by a complex set of design rules. The process of converting the specifications of an electrical circuit into a layout is called the ph
Aleshin Stanislav V.
Andreev Alexander E.
Jones Edwin R.
Kapoor Ashok K.
Koford James S.
Jackson Jerome
LSI Logic Corporation
Mitchell Silberberg & Knupp LLP
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