Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Having heterojunction
Reexamination Certificate
2001-12-27
2004-08-31
Thomas, T. (Department: 2815)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Having heterojunction
C438S338000, C438S342000, C438S343000
Reexamination Certificate
active
06784064
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of making a heterojunction bipolar transistor and a compound semiconductor heterojunction bipolar transistor.
2. Related Background Art
Heterojunction bipolar transistors (HBTs) have a high current gain and are excellent in high-frequency characteristics, whereby they have been utilized as amplifiers for transmitters and receivers in high-speed optical communication systems. HBTs exhibit these excellent characteristics because their emitter region is constituted by a semiconductor material having an energy band gap (Eg) greater than that of their base region. The heterojunction allows the emitter injection efficiency to increase even when the carrier concentration of the base region is made high.
SUMMARY OF THE INVENTION
The inventors have been studying heterojunction bipolar transistors which are excellent in high-frequency characteristics. The inventors' investigations have revealed that there are various causes which deteriorate high-gain characteristics and high-frequency characteristics of heterojunction bipolar transistors. Various improvements for eliminating these causes have been proposed for heterojunction bipolar transistors. For example, Japanese Patent Application Laid-Open Nos. 05-48078 and 08-139101 publications disclose heterojunction bipolar transistors.
FIG. 13A
is a plan view showing an example of the structure of a heterojunction bipolar transistor utilized by the inventors for consideration.
FIG. 13B
is a sectional view taken along the line VI—VI in
FIG. 13A. A
mask layer for etching is formed on an epitaxially grown emitter layer. The mask layer has a rectangular form. Anisotropic wet etching is carried out by using this mask layer to form an emitter
61
. The emitter
61
of this transistor has an inverted mesa structure at a pair of its sides. When the emitter
61
is formed by anisotropic wet etching, the etching rate however varies depending on the orientation of crystals, so that the emitter region
61
has a hexagonal form as shown in FIG.
13
A. In
FIG. 13A
, the angle indicated by reference symbol E becomes 90 degrees due to the crystal orientation of semiconductor material of emitter. In this transistor, a wiring lead
63
connects an emitter electrode
62
on the emitter region
61
to another circuit. The emitter
61
of the transistor is hexagonal and the wiring lead
63
extends in the longitudinal direction of the emitter region
61
, so that the lead
63
is arranged to pass over the corner indicated by reference symbol E. In this arrangement, a greater stress occurs in the vicinity of the angle part E than in other parts of the wiring lead
63
. Since the reliability tends to deteriorate due to this stress, it will take a long period to secure acceptable reliability.
When the emitter has a hexagonal form, the base area disposed under the emitter is inevitably larger. When the area of the base is large, the junction capacitance between the base and the collector disposed under the base (hereinafter referred to as base-collector capacitance) increases. When the junction capacitance increases, the operating speed of HBT decreases.
Japanese Patent Application Laid-Open No. 05-243257 publication discloses an emitter disposed so as to orient in [
001
] direction. In this configuration, the emitter region has a rectangular form and can solve the problem mentioned above. According to the inventors' investigations, however, the emitter region has no side of inverted mesa structure. In order to form an emitter electrode and base electrodes by a self-alignment process in this configuration of the HBT, it is necessary that side faces of the emitter region be etched after an emitter cap layer is formed on the emitter.
Therefore, it is an object of the present invention to provide a method of making a heterojunction bipolar transistor which is excellent in high-frequency characteristics, and a heterojunction bipolar transistor.
In one aspect, the present invention relates to a method of making a heterojunction bipolar transistor. This method comprises the steps of: (a) making a mask layer on a compound semiconductor layer with a photomask for forming an emitter; and (b) forming an emitter region by wet-etching the compound semiconductor layer with the mask layer. The photomask has a pattern thereon for forming the emitter region. The pattern is constituted by a first area part associated with a shape of the emitter to be formed, and a plurality of second area parts. Each of the second area parts includes first and second sides that meet each other to form an acute angle therebetween, and a third side in contact with the first area part.
In another aspect, the present invention relates to a method of making a heterojunction bipolar transistor. This method comprises the step of: (a) forming on a compound semiconductor layer a mask layer for forming an emitter; and (b) forming an emitter region by wet-etching the compound semiconductor layer with the mask layer. The mask layer has a pattern for forming the emitter region. The pattern has a first pair of edges extending in a predetermined direction, a second pair of edges extending in a direction intersecting the predetermined direction, and a mask part projecting from at least one edge of the first pair of edges. The mask part has an edge portion extending in a direction of a line inclined toward the edge of the first pair of edges.
In still another aspect, the present invention relates to a heterojunction bipolar transistor. This transistor comprises a collector, abase, and an emitter. The transistor has a first mesa including the collector and the base, and a second mesa including the emitter. The emitter is provided on the first mesa and contains a compound semiconductor. The emitter has a first pair of sides extending in a predetermined direction, and a second pair of sides extending in another direction intersecting the predetermined direction. The first pair of sides of the emitter are provided with an inverted mesa structure, whereas the second pair of sides thereof are provided with a normal mesa structure.
The present invention will be more fully understood from the detailed description given hereinbelow and the accompanying drawings, which are given by way of illustration only and are not to be considered as limiting the present invention.
Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will be apparent to those skilled in the art from this detailed description.
REFERENCES:
patent: 4801986 (1989-01-01), Chang et al.
patent: 5614423 (1997-03-01), Matsuoka et al.
patent: 6333236 (2001-12-01), Koganei
patent: 5-48078 (1993-02-01), None
patent: 5-243257 (1993-09-01), None
patent: 8-139101 (1996-05-01), None
patent: 10050720 (1998-02-01), None
Kotani Kenji
Yaegashi Seiji
Yanagisawa Masaki
Yano Hiroshi
Brock II Paul E
Smith , Gambrell & Russell, LLP
Sumitomo Electric Industries Ltd.
Thomas T.
LandOfFree
Heterojunction bipolar transistor and method of making... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Heterojunction bipolar transistor and method of making..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Heterojunction bipolar transistor and method of making... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3301817