Heterogeneous programmable gate array

Details Heterogeneous programmable gate array Heterogeneous programmable gate array

2000-05-05

2002-08-13

Le, Don Phu (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S041000

Reexamination Certificate

active

06433578

ABSTRACT:

BRIEF DESCRIPTION OF THE INVENTION
This invention relates generally to programmable logic devices. More particularly, this invention relates to heterogeneous programmable gate arrays.
BACKGROUND OF THE INVENTION
Programmable logic devices are widely used in the electronics industry. Contemporary programmable logic devices typically comprise an homogeneous, general-purpose logic array. Also, contemporary use typically requires various programmable logic devices to serve multiple purposes. Instead of designing specific gate arrays for each purpose, multiple homogeneous programmable gate arrays are programmed to serve each required purpose. Field programmable gate arrays (FPGAs) are typically used for these purposes.
To date, the relevant industry has significantly invested in developing “optimum” homogeneous architectures that can be programmed to serve most purposes. Using homogeneous FPGAs can be very inefficient when the programmed logic function is complex or when the programmed logic function properties are heterogeneous in nature. Inefficient device utilization results when inevitably parts of the homogeneous architecture will be wasted because they are not needed for a specific purpose. As shown with line
20
in
FIG. 1
, random/control logic functions will only result in high utilization when implemented in minimal structure devices, whereas, as shown with line
22
, structured/datapath logic functions will only result in high utilization when implemented in maximal structure devices. For example, parity trees and state machines have high utilization in minimal structure arrays, and arithmetic and register file functions have high utilization in maximal structure arrays. However, in a minimal structure device, utilization efficiency drastically decreases as the degree of implemented function structure increases. Conversely, in a maximal structure device, utilization efficiency drastically decreases as the degree of implemented function structure decreases. Random/control and structured/datapath are complementary, heterogeneous properties.
FPGAs typically comprise a homogeneous logic block array suitable for implementing some random/control and some structure/datapath functions. Further, current practices often use separate devices for unstructured logic and structured logic functions. The use of separate devices requires increased manufacturing and packaging costs as well as a relatively large amount of space when mounted on a circuit board. The spatial inefficiency reduces computational speed as signals are passed between resources.
In view of the foregoing, it would be highly desirable to provide an improved programmable logic device that has unstructured logic and structured logic resources on the same device.
SUMMARY OF THE INVENTION
A heterogeneous programmable gate array (HPGA) comprises two or more arrays. In the preferred embodiment, a HPGA comprises at least one unstructured logic array and at least one structured logic array. An unstructured input/output interconnect structure delivers unstructured-to-unstructured input/output signals to the unstructured logic array, while a bussed input/output interconnect structure delivers structured-to-structured input/output signals to the structured logic array. A control signal bus is functionally connected between the unstructured logic array and the structured logic array to deliver unstructured source signals therebetween. A bussed signal bus is functionally connected between the unstructured logic array and the structured logic array to deliver structured source signals therebetween.
A logic function is “unstructured” if either the type of logic or routing resources required to implement the function does not exhibit regularity or uniformity. For example, a state machine comprises various state functions in which a next-state function is typically independent of other state functions; thus, various states in the state machine are typically not physically aligned with each other. A logic function is “structured” if the logic and routing resources required to implement the function exhibit regularity or uniformity. For example, a datapath object, such as a loadable counter, comprises a repetition of a bit-slice function. In other words, the next-state function is typically identical for all the bit-slice functions. Further, each bit slice receives the same clock-enable and load control signals; thus, each bit has an inherent relationship with respect to each other and should be physically aligned with each other. For example, bit i should be situated between bit i−
1
and i+
1
. Generally, unstructured logic is the complement of structured logic.
In another exemplary embodiment, a heterogeneous programmable array comprises sections having at least two sub-sections that have complementary logic and route resource properties. The sub-sections are configured to specifically optimize the complementary logic, such as unstructured/control logic and structured/datapath logic, respectively. In a preferred embodiment, the sub-sections are configured to include approximately one-third unstructured/control logic and approximately two-thirds structured/datapath logic. The unstructured/control logic is generally fine-grained, short, with low-fanout, and high-skew. The structured/datapath logic is generally medium-grained, long, with high-fanout, and low-skew. Examples of unstructured/control logic are glue logic, decoders, parity trees, and state machines. Examples of structured/datapath logic are registers, arithmetic devices, register files, random access memories, and first-in-first-out modules.
The device in accordance with the invention provides a platform for disparate programmable logic and routing resources. The topology facilitates superior partitioning of contemporary netlists. That is, logic netlists can be partitioned into fragments targeting specific array resources. Appropriate partitioning results in significantly increased device utilization and system performance. In addition, the apparatus improves overall device efficiency because arrays can be optimized for specific purposes.


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