Heterogeneous parallel multithread processor (HPMT) with...

Electrical computers and digital processing systems: processing – Processing control – Context preserving (e.g. – context swapping – checkpointing,...

Reexamination Certificate

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C718S108000

Reexamination Certificate

active

11064795

ABSTRACT:
The invention relates to a heterogeneous parallel multithread processor (1) with shared contexts which has a plurality (M) of parallel-connected standard processor root unit types (2p; p∈ [1, . . . , M]), where each respective standard processor root unit type (2p) has at least one or more (K) parallel-connected standard processor root units (2pq; q∈ [1, . . . , K]) for instruction execution of program instructions from various threads (T), each standard processor root unit type (2p) having N local context memories (32pt) which each buffer-store part of a current processor state for a thread. The multithread processor (1) also has a plurality (N) of global context memories (3t; t∈ [1, . . . , N]) which each buffer-store part of a current processor state for a thread, and a thread control unit (4) which can connect any standard processor root unit (2pq) to any global context memory (3t).

REFERENCES:
patent: 5361337 (1994-11-01), Okin
patent: 6779182 (2004-08-01), Zolnowsky
patent: 6915414 (2005-07-01), Yearsley et al.
patent: 10353268 (2005-07-01), None
Kumar et al., “Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction,”Proceedings of 36thAnnual IEEE/ACM International Symposium on Microarchitecture, Dec. 2003, pp. 81-92.
Ungerer et al., “A Survey of Processors with Explicit Multithreading,”ACM Computing Surveys, ol. 35, No. 1, Mar. 2003, pp. 29-63.
German Office Action dated Nov. 2, 2004, no translation.
German Office Action dated Jul. 21, 2006, no translation.

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