Electronic digital logic circuitry – Multifunctional or programmable – Significant integrated structure – layout – or layout...
Reexamination Certificate
1999-10-12
2003-07-08
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Significant integrated structure, layout, or layout...
C326S041000, C326S101000, C257S499000, C257S503000, C333S012000
Reexamination Certificate
active
06590419
ABSTRACT:
This invention relates to programmable logic devices (PLDs) and more particularly to an improved interconnect architecture for such devices.
BACKGROUND OF THE INVENTION
Programable Logic Devices (PLDs) are a widely used form of integrated circuit due to the flexibility provided by their customizable nature. In general PLDs include field programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), simple programmable logic devices and laser programmable devices. Architecturally a PLD includes logic blocks and input/output (I/O) blocks, which are connectable through a programmable interconnect structure or network.
A typical PLD is an integrated circuit chip that, wholly or in part, consists of an array of one or more logic blocks, I/O and a programmable routing or interconnect network that can be programmed by a user to provide an interconnection between the logic blocks and I/O circuits to achieve a desired logic function. The PLD can be a standalone device or be embedded in a larger integrated circuit such as ASICs or the like. Exemplary forms of such devices are disclosed in U.S. Pat. No. 5,825,202 and U.S. Pat. No. 5,687,325.
The logic blocks may be comprised of a fixed logic function or may in turn also have programable interconnections or functionality. The logic blocks may be further broken down as sub-blocks or grouped together as a cluster of blocks. The blocks may also include input/output circuits. Typically the I/O circuits enable connection of the chip to external circuits or to other parts of the chip as in the case of embedded FPGAs. The I/O blocks are typically arranged at the periphery of a chip. A PLD is normally arranged as a regular array of logic blocks each of which may be identical or may be of several different types such as RAM blocks, Look-Up-Table based blocks, P-term based blocks etc. The conductors of the programmable interconnect network array are typically arranged along rows and columns defined by the array of logic blocks as shown schematically in FIG.
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The interconnect structure of the PLD consists of pre-fabricated wires and pre-fabricated switches which can be programmed to electrically connect different logic blocks to provide a desired function. The connections between the conductors (wires) and the logic blocks and between different wire segments is implemented by means of programmable switches at predetermined interconnection points. The programmable switches may be implemented as pass-transistors, tri-state buffers, fuses, antifises or combinations thereof. Laser programing of interconnections may also be achieved by burning off the metal conductors at desired locations. In some cases a switch state can be controlled by a Static or Dynamic Random Access Memory (SRAM or DRAM), Read Only Memory (ROM), Electrically Programmable Read Only Memory (EPROM), Electrically Erasable and Programmable Read Only Memories (EEPROMs), Flash memory or any other variation or combination of the above memory. Various types of switches are well known in the art and are described for example in U.S. Pat. No. 4,870,302 and U.S. Pat. No. 5,955,751 to list a few.
There are a number of tradeoffs involved in the design of PLDs. A PLD designer or architect is constrained by various operational parameters such as speed of circuits implemented in the PLD, semiconductor or silicon area required for a given logic capacity, power dissipation of the PLD once it has been programmed by a user, reliability (e.g. low glitch probability) and routing flexibility. A PLD architect cannot know before hand all the many uses for which a user may program the device. Thus PLDs are designed to be as general as possible.
For example, a PLD architect's objective may be to minimize the surface area of the PLD while maximizing the logic capacity. That is, maximize the number of and functionality of logic blocks and provide sufficient interconnect resources and flexibility to allow as broad a range of circuit implementations as possible. Another design objective may be to maximize the speed of circuits implemented in the PLD while minimizing the surface area, logic and interconnect resources required to implement the circuits. For example, a PLD architect knows that speed can be improved by reducing the number of programmable connection switches, but this comes at the expense of routing flexibility. Reliability, in terms of glitch prevention can be improved by spacing interconnect wires further apart, but this comes at the expense of area.
Consequently, one area of focus in PLD architecture design is the interconnect network architecture, where the objective is to minimize the surface area required for the interconnect resources while maximizing the speed and minimizing the PLD resources required to implement circuits on the PLD. The interconnect architecture here refers to interconnect conductors, the programmable switches and the interface between them and the logic blocks. The reader is referred to U.S. Pat. No. 5,907,248, which provides a background on various interconnection architectures and improvements thereto.
However, circuits that are implemented in PLDs tend to have different parts with different requirements. For example, some critical paths of the circuit have to be fast to meet timing requirements, some parts (e.g. clock signals) need to be glitch free and parts which are not speed sensitive should use as little silicon area or PLD resources as possible.
Most PLD architectures do not take into account this circuit heterogeneity. Most of the prior ant use a homogenous interconnection architecture wherein parameters such as wire widths, spacing between wires, dimensions of the transistors used in the buffets and switches, interface circuits between the wires/switches and the logic blocks are constant throughout the PLD. Furthermore homogenous architectures are easier for the CAD tools that are used to map circuit descriptions into the PLD architecture.
Current interconnect architectures have considered varying a single parameter in order to optimize the PLD. For example Actel's U.S. Pat. No. 5,073,729, Altera's U.S. Pat. No. 5,900,743 and Xilinx U.S. Pat. No.'s 5,801,546 and U.S. Pat. No. 5,907,248, describe PLD architectures in which optimization is limited to using different lengths of interconnect wires. On the other hand, U.S. Pat. No. 5,942,913 describes an interconnect structure using a mixture of buffered and unbuffered interconnect lines. In both cases, optimization is limited to just one parameter.
However, these architectures are limited in that they do not offer a user sufficient flexibility when designing a circuit that requires different PLD interconnect resources for different parts of the circuit. For example in U.S. Patent No. 5,900,743 horizontal conductors of many different lengths makes it possible to make interconnections between horizontally aligned logic regions using conductors that are close to the appropriate lengths for making that connection.
Accordingly there is a need for an improved PLD architecture that is optimised in terms of one or more selected operational parameters such as speed, power, area, flexibility and reliability, while minimizing the impact on the remaining parameters.
SUMMARY OF THE INVENTION
An advantage of the present invention is the provision of a PLD architecture that is optimized for a selected one or more operational parameters, while minimizing the impact on the remaining parameters. For example the operational parameters may include speed, area, power, reliability and flexibility.
In accordance with this invention there is provided a PLD comprising:
(a) one or more function blocks; and
(b) a plurality of groups of interconnect resources each group of a selected type for programmable connection to one or more of the function blocks, and wherein a first number of at least one type of interconnect resources being optimized for a first operational parameter of the PLD and a second number of the same type being optimized for a second operational parameter.
In a further embodiment of the
Betz Vaughn
Rose Jonathan
Altera Toronto Co.
Fish & Neave
Tan Vibol
Tokar Michael
Tuma Garry J.
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