Hermetic chip scale packaging means and method including...

Semiconductor device manufacturing: process – Making device or circuit responsive to nonelectrical signal – Physical stress responsive

Reexamination Certificate

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Details

C438S052000, C438S053000

Reexamination Certificate

active

06638784

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to integrated circuit (IC) chips, and more particularly relates to such chips having micro-electro-mechanical-systems (MEMS) included thereon, and even more particularly relates to hermetic packaging of such MEMS.
In the past, MEMS have been included on chips for numerous reasons, and MEMS have provided much functionality.
While use of the MEMS on chips has some beneficial aspects, it does have serious drawbacks. The MEMS become damaged during conventional wafer processing steps and as a result, they are typically bonded to a chip individually at the chip level. This chip level processing of MEMS is time consuming and relatively expensive.
Consequently, there exists a need for improved IC chips having MEMS thereon and for improved methods of manufacturing the same.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an improved hermetic MEMS chip package.
It is a feature of the present invention to include a hermetic cap bonded to a wafer containing numerous chips with MEMS thereon.
It is an advantage of the present invention to eliminate the need for capping of MEMS individually at the chip level.
It is another object of the present invention to provide for self-test capability of MEMS.
It is another feature of the present invention to include piezo-resistive pressure sensor for sensing pressure around the MEMS.
It is another advantage of the present invention to sense a pressure change as a result of a hermetic packaging failure.
The present invention is a hermetic MEMS chip package and method for processing the same, which is designed to satisfy the aforementioned needs, provide the previously stated objects, include the above-listed features and achieve the already articulated advantages.
Accordingly, the present invention is a hermetic MEMS chip package and method which includes providing a hermetic cap over a wafer containing numerous MEMS chips thereon.


REFERENCES:
patent: 4430895 (1984-02-01), Colton
patent: 5668033 (1997-09-01), Ohara et al.
patent: 5837562 (1998-11-01), Cho
patent: 5837935 (1998-11-01), Carper et al.
patent: 6062461 (2000-05-01), Sparks et al.
patent: 6100108 (2000-08-01), Mizuno et al.
patent: 6180435 (2001-01-01), Ise et al.
patent: 6235612 (2001-05-01), Wang et al.
Dirk De Bruyker, “A Combiner Piezoresistive/ . . . Pressure Senson with Self Test . . . ”, 1997 IEEE, 1461-1464.*
Liwel Lin, “MEMS Pressure Sensors . . . ”, 1998 IEEE, 429-436.*
Cheng gui Hou, “A Pressure Sensor Made of Two Pieszoresistive Bridges”, 1996 IEEE.

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