Heaviest only fail potential

Data processing: measuring – calibrating – or testing – Measurement system in a specific environment – Quality evaluation

Reexamination Certificate

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C438S014000, C700S121000, C324S765010

Reexamination Certificate

active

06658361

ABSTRACT:

FIELD
This invention relates to the field of yield prediction in a manufacturing environment. More particularly the invention relates to identifying a fail potential of a type of defect or of a part with defects.
BACKGROUND
During each step in an integrated circuit manufacturing process, defects may be introduced to the integrated circuit. For the specific example of the semiconductor industry, defects tend to be continuously introduced to the integrated circuits on a silicon wafer as it is processed. Some defects as are so insignificant that they alone do not cause operational failure of an integrated circuit, although a large number of singularly insignificant defects may in combination cause the failure of the integrated circuit. Some defects, however, are large enough to be the sole cause of the failure of the integrated circuit.
Currently, there are two widely implemented approaches to estimating the fail potential of an integrated circuit. In one approach, every identifiable defect in an integrated circuit, whether the defect be large or small, at each step in the manufacturing process is factored into the estimation of fail potential. In another approach, only those integrated circuits having a single defect are considered in estimating the fail potential. Both of these approaches have disadvantages. In the first, a significant amount of data is generated, but the results tend to be inaccurate and misleading because of the consideration of so many small defects that contribute little to the final result. In the second approach, there are typically so very few integrated circuits having only a single defect, that there tends to be a scarcity of data to use in calculating the fail potential. This causes low confidence in the results.
Thus, there are problems inherent with the known approaches to gauging integrated circuit quality as described above. What is needed, therefore, is a system for determining the fault potential of a type of defect with a high level of confidence and using minimal empirical data.
SUMMARY
The above and other needs are met by a method for determining an effective fatal defect count based on defects in a plurality of inspected integrated circuits. The method includes acquiring defect information related to defects in the inspected integrated circuits, and assigning defect weight values to each of the defects based on the defect information. Preferably, the defect weight values are in N number of defect weight value ranges, including a lowest defect weight value range and highest defect weight value range. For each integrated circuit, a heaviest defect is determined, where the heaviest defect is the defect on each integrated circuit having a highest defect weight value. For each of the N number of defect weight value ranges, a total number T(n) of the heaviest defects having a defect weight value within each defect weight value range n is determined, where n equals one to N. The method includes determining a weighted total defect count T
W
(n), for n equals one to N, by weighting the total number T(n) for each of the defect weight value ranges according to a weighting function FP(n) which approaches zero at the lowest defect weight value range and approaches one at the highest defect weight value range. The method also includes determining an effective fatal defect count by summing the values of T
W
(n) for the N number of defect weight value ranges.
In various preferred embodiments of the method, the defect weight values are assigned to each of the defects based on defect size, where defects having a smallest size are in the lowest defect weight value range, and defects having a largest size are in the highest defect weight value range. Most preferably the integrated circuits are dice on a silicon wafer. The defect information is preferably collected during in line tests and at final test, such as at wafer sort. Most preferably, the steps other than acquiring the defect information are accomplished at a later point in time on a computerized analyzer.
The “heaviest only” weighting provided by the invention gives more weight to large defects than to small defects. Thus, the effective fatal defect count is weighted more heavily toward larger defects. Gauging yield based on an effective fatal defect count determined by heaviest only filtering, rather than based solely on the total number of defects, provides a better prediction of yield. In this manner, the present invention provides a more accurate indicator of future yield than has been previously available.
In some preferred embodiments, the method according to the invention includes determining a total number T
D
of the inspected integrated circuits, and determining a total number T
G
of inspected integrated circuits which pass electrical testing. The method also includes acquiring defect information related to defects in the inspected integrated circuits, and assigning defect weight values to each of the defects based on the defect information, where the defect weight values are within N number of defect weight value ranges. For each integrated circuit, a heaviest defect is determined, where the heaviest defect is the defect on each integrated circuit having a highest defect weight value. For each of the N number of defect weight value ranges, a total number T(n) of the heaviest defects having a defect weight value within a defect weight value range n is determined, where n equals one to N. A total number T
G
(n) of the inspected integrated circuits which pass electrical testing though having a heaviest defect with a defect weight value falling within the defect weight value range n is also determined, where n equals one to N. A fail potential value FP(n) is calculated based on T
D
, T(n), T
G
, and T
G
(n), and an effective fatal defect count EFDC is calculated according to:
EFDC
=

n
=
1
N



(
T



(
n
)
×
FP



(
n
)
)
.
In some preferred embodiments, the weighting function FP(n) is determined according to:
FP



(
n
)
=
1
-
(
T
G



(
n
)
T



(
n
)
)
(
T
G
-
T
G



(
n
)
T
D
-
T



(
n
)
)
for each of the N number of defect weight value ranges.


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patent: 6265232 (2001-07-01), Simmons
patent: 6324481 (2001-11-01), Atchison et al.
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patent: 6456951 (2002-09-01), Maeda et al.
patent: 6487511 (2002-11-01), Wooten
patent: 6496788 (2002-12-01), Kikuchi
patent: 2001/0023083 (2001-09-01), Simmons
patent: 2001/0051836 (2001-12-01), Lamey et al.
patent: 2002/0032888 (2002-03-01), Ott et al.
patent: 2002/0142522 (2002-10-01), Pnueli et al.
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patent: 2003/0017664 (2003-01-01), Pnueli et al.
patent: 2003/0120445 (2003-06-01), Barbour et al.
Merino et al. “SmartBit: Bitmap to defect correlation software for yield improvement”, IEEE, 2000.*
Nurani, “Effective Defect Management Strategies for Emerging Fab Needs”, IEEE, 2001.*
Bichebois et al., “Analysis of Defect to Yield Correlation on Memories: Method, Algorithms and Limits”, IEEE, 1997.*
Yoshitake et al., “Defect Control Using an Automatic Killer Defect Selection Method”, IEEE, 1998.*
Ross, R. & Atchison, N., TI Technical Journal “The Calculation of Wafer Probe Yield Limits from In-Line Defect Monitor Data”, Oct., 1998.
Kasten A. Zalnoski, J., and Mullenix, P., Semiconductor International “Calculating Defect Limited Yields From In-Line Inspections”, Jul., 1997.

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