Single-crystal – oriented-crystal – and epitaxy growth processes; – Processes of growth with a subsequent step of heat treating...
Reexamination Certificate
1998-12-16
2003-04-22
Utech, Benjamin L. (Department: 1765)
Single-crystal, oriented-crystal, and epitaxy growth processes;
Processes of growth with a subsequent step of heat treating...
Reexamination Certificate
active
06551398
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to a heat treatment method for a silicon monocrystal wafer obtained by slicing a silicon monocrystal ingot grown by a Czochralski method (hereinafter referred to as “CZ method”), and a silicon monocrystal wafer wherein crystal defect density is significantly reduced by the method.
2. Description of the Related Art
As a method for eliminating crystal defects of a silicon monocrystal wafer, there has been adopted a method in which a wafer is subjected to hydrogen anneal at a high temperature. In this method, oxide precipitate is intentionally reduced with hydrogen and dissolved, and thus surface oxide-film is eliminated, resulting in increasing oxygen out-diffusion speed, so that defects can be eliminated. However, it is known that even if the hydrogen anneal is performed under the typical condition that a temperature is 1200° C. and treatment time is 60 minutes, since crystal defects and oxide precipitates remain near the surface of the wafer, oxygen is continuously out-diffused from inside to outside, and oxide precipitates are re-formed. Further, this method strongly depends on history of crystal before hydrogen anneal treatment, and therefore the wafer having less crystal defects has been selected as a wafer which is to be subjected to hydrogen anneal treatment.
As an another method, there has been adopted a method in which crystal defects are eliminated by lowering a growth rate of monocrystal. However, according to this method, although the number of crystal defects can be decreased, electronic characteristics such as oxide dielectric breakdown voltage of a device are degraded since the size of the defect is increased.
As described above, it is difficult to eliminate crystal defects sufficiently, even when the silicon monocrystal wafer is subjected to hydrogen anneal. Furthermore, lowering the pulling rate results in increase of the defect size, and therefore it is difficult to eliminate defects with hydrogen anneal.
Meanwhile, COPs (Crystal Originated Particles) have recently been cited as a cause of decreasing the yield of a device-fabricating process. COP is one type of crystal defects that are introduced in a crystal during the growth thereof and is known to be a defect of vacancy type having a regular octahedron structure void or cavity.
When a silicon wafer having COPs subjected to mirror-polishing is cleaned through use of a mixture solution of ammonia and hydrogen peroxide, pits are formed in the wafer surface. When the number of particles on the wafer is measured through use of a particle counter, pits are also detected and counted as particles together with real particles. The thus-detected pits are called “COPs” in order to distinguish them from the actual particles.
COPs existing at the surface layer portion of a wafer degrade the electric characteristics of the wafer. For example, a time dependent dielectric breakdown (TDDB) of oxide film, one important electric characteristic of a semiconductor device determined through a reliability test, is known to be related to COPs, and therefore reduction of COPs is required in order to improved the time dependent dielectric breakdown.
Also, COPs are said to affect an ordinary time zero dielectric breakdown (TZDB) of oxide film.
Moreover, COPs are said to adversely affect the device-fabricating process. For example, if COPs exist at the surface layer portion of a SOI (Silicon On Insulator) wafer, buried oxide film is etched by etchant or atmosphere gas passed through the COPs during an etching process or a heat treatment process, and a step is formed during a wiring process, and the thus-formed step causes breakage of wiring, resulting in a decrease in yield.
A hydrogen anneal is known as a method for reducing the COPs. However, even if anneal is conducted under the typical treatment condition, COPs at the surface layer portion of the wafer can not be completely eliminated, but partly remain. Furthermore, COPs also remain at relatively near area to the surface.
The reason of why COPs at the surface layer portion of the wafer can not be completely eliminated is, for example, that COPs remain in the wafer even when high temperature hydrogen anneal is conducted at 1200° C., for 60 minutes, and later, internal COPs come to appear on the surface as a result of that the surface is etched during hydrogen anneal. COPs which come to appear on the surface right before the temperature begins to be lowered are difficult to be eliminated while the temperature is falling, and the COPs which come to appear on the surface while the temperature is falling are more difficult to be eliminated. In order to prevent COPs from appearing while the temperature is falling, it is necessary to raise the temperature falling rate.
Because, silicon is generally etched in a thickness of about 0.5 &mgr;m through hydrogen anneal at 1200° C. for 60 minutes, and etching rate decreases and migration on the surface of the silicon get small, as temperature lowers. And therefore, COP appearing on the surface while the temperature is lowering is not etched, and is difficult to be eliminated.
Alternatively, in order to reduce COPs, it is necessary to prepare a wafer having COPs which can be easily eliminated by hydrogen anneal, and for that purpose, it is necessary to study thoroughly the condition for pulling silicon monocrystal ingot which is to be used for preparation of a wafer. In the prior art, a growth rate of monocrystal is lowered in order to reduce defects such as COP. However, in this case, although the number of COP can be decreased, the size thereof gets large, and therefore, the probability that COPs are not eliminated is high even if the wafer prepared from the monocrystal ingot thus obtained is subjected to hydrogen anneal. Therefore, it is difficult to eliminate COP defects by the existing technique.
SUMMARY OF THE INVENTION
The present invention has been accomplished to solve the above-mentioned problems, and an object of the present invention is to manufacture a silicon monocrystal wafer in which crystal defects existing on the surface of the wafer or at the surface layer portion thereof are minimized, and to provide a silicon monocrystal wafer for a device which is excellent in not only oxide dielectric breakdown voltage but also other electric characteristics such as electrical reliability.
Another object of the present invention is to enable production of a silicon monocrystal wafer having no defect, and to achieve enhancement of productivity, reduction in the amount of hydrogen to be used, cost reduction, and the like.
To achieve the above object, the present invention relates to a heat treatment method for a silicon monocrystal wafer comprising the steps of heat-treating in a reducing atmosphere a silicon monocrystal wafer manufactured by slicing a silicon monocrystal ingot which is grown by Czochralski method wherein a wafer obtained by slicing a silicon monocrystal ingot having oxygen concentration of 16 ppma or less which is manufactured by pulling at a growth rate of 0.6 mm/min or more, and in which COPs exist in high density is subjected to anneal heat treatment at 1200° C. or above for one second or more through use of a rapid heating/rapid cooling apparatus.
The rapid heating/rapid cooling means, for example, a method that a wafer is immediately loaded into a heat treatment furnace in which a temperature is arranged in the above-mentioned range, and is immediately loaded out upon elapse of the above-mentioned heat treatment time, or a method that a wafer is immediately subjected to heat treatment with a lump heater or the like after it is arranged at a predetermined position in the heat treatment furnace. The language reading “immediately loaded into” or “immediately loaded out” means that there are not performed an operation for raising and lowering the temperature over a certain period, as well as a conventional so-called loading or unloading operation in which a wafer is slowly loaded into the heat treatment furnace and slowly loaded out. Of course
Abe Takao
Kato Masahiro
Kobayashi Norihiro
Anderson Matthew A.
Hogan & Hartson LLP
Shin-Etsu Handotai & Co., Ltd.
Utech Benjamin L.
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