Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-01-03
2002-11-05
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S350000
Reexamination Certificate
active
06476446
ABSTRACT:
TECHNICAL FIELD
The present invention generally relates to improved Silicon-on-Insulator devices. More particularly, the present invention relates to methods for removing heat from Silicone-Insulator devices and devices having such characteristics.
BACKGROUND ART
Silicon-on-Insulator (SOI) technology is of growing importance in the field of integrated circuits. SOI technology involves forming transistors in a relatively thin layer of semiconductor material overlying a layer of insulating material. More particularly, SOI technology is characterized by the formation of a thin silicon layer (device region) for formation of the active devices over an insulating layer, such as an oxide, which is in turn formed over a substrate. Transistor sources and drains are formed, for example, by implantations into the silicon layer while transistor gates are formed by forming a patterned oxide and conductor layer structure.
Such structures provide a significant gain in performance by having lower parasitic capacitance (due to the insulator layer) and increased drain current due to floating body charging effects (since no connection is made to the channel region and charging of the floating body provides access towards a majority of carriers which dynamically lower the threshold voltage, resulting in increased drain current). Devices, such as metal oxide silicon field effect transistors (MOSFET), have a number of advantages when formed on SOI wafers versus bulk silicon MOS transistors. These advantages include: reduced source/drain capacitance and hence improved speed performance at higher-operating frequencies; reduced N
+
to P
+
spacing and hence higher packing density due to ease of isolation; absence of latchup; lower voltage applications; and higher “soft error” upset immunity (i.e., the immunity to the effects of alpha particle strikes).
Although there are significant advantages associated with SOI technology, there are significant disadvantages as well. For example, poor heat removal from devices on an SOI substrate is a significant disadvantage. Electrical devices generate heat, and the inability to remove or dissipate the heat results in poor and/or inconsistent performance of the electrical devices, or even in some instances device and/or substrate degradation.
There is poor heat removal for devices on SOI substrates primarily because of the oxide insulation layer. More specifically, the oxide insulation layer has a markedly lower thermal conductivity than the thermal conductivity of conventional bulk silicon (typically used as semiconductor substrates), which typically surrounds semiconductor devices. As a result, the buried oxide layer undesirably insulates thermally the device region in SOI substrates. This problem is in some instances compounded when shallow trench isolation areas are formed within an SOI substrate. Nevertheless, shallow trench isolation areas offer desirable characteristics to semiconductor substrates containing such regions.
In view of the aforementioned disadvantages, there is a need for SOI devices of improved quality, particularly SOI devices having improved heat removal characteristics, and more efficient methods of making such SOI devices.
SUMMARY OF THE INVENTION
As a result of the present invention, an SOI substrate having improved heat removal characteristics (from the device layer) is provided. By forming an SOI substrate according to the present invention, improved performance of devices subsequently formed on the SOI substrate is facilitated. Moreover, forming an SOI substrate in accordance with the present invention does not degrade or deleteriously effect the advantageous properties and characteristics commonly associated with SOI technology (improved speed performance at higher-operating frequencies, higher packing density, absence of latch-up, lower voltage applications, and higher “soft error” upset immunity). The SOI substrates in accordance with certain embodiments of the present invention also have desirable characteristics commonly associated with shallow trench isolation areas.
In one embodiment, the present invention relates to a method of forming an SOI substrate involving providing a structure comprising a bulk silicon layer, a buried insulation layer over the bulk silicon layer, a silicon device layer over the buried insulation layer, and a mask layer over the silicon device layer; etching portions of the mask layer, the silicon device layer, and the buried insulation layer thereby forming openings and exposing portions of the bulk silicon layer; depositing polysilicon in the openings; removing a portion of the polysilicon in the openings to form polysilicon sidewalls adjacent the silicon device layer and the buried insulation layer and to form gaps at least partially surrounded by the polysilicon sidewalls; depositing an insulation material in the gaps; and removing the mask layer.
In another embodiment, the present invention relates to a method of increasing heat removal in an SOI substrate, involving providing a structure comprising a bulk silicon layer, a buried silicon dioxide layer over the bulk silicon layer, a silicon device layer over the buried silicon dioxide layer, and a mask layer over the silicon device layer; anisotropically etching portions of the mask layer, the silicon device layer, and the buried silicon dioxide layer thereby forming openings and exposing portions of the bulk silicon layer; depositing polysilicon in the openings over the bulk silicon layer; removing a portion of the polysilicon in the openings to form polysilicon sidewalls adjacent the silicon device layer and the buried silicon dioxide layer and in contact with the bulk silicon layer, wherein the remaining portion of the polysilicon in the openings forms gaps; depositing an insulation material in the gaps; and removing the mask layer.
In yet another embodiment, the present invention relates to an SOI substrate made of a bulk silicon layer, a buried insulation layer over the bulk silicon layer, a silicon device layer over the buried insulation layer; a plurality of at least one of holes and trenches in the silicon device layer and the buried insulation layer, wherein the plurality of at least one of holes and trenches contains a polysilicon sidewall adjacent the bulk silicon layer, the buried insulation layer, and the silicon device layer, the polysilicon sidewall surrounding an insulating material, the insulating material in contact with the bulk silicon layer.
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Advanced Micro Devices , Inc.
Amin & Turocy LLP
Thomas Tom
Vu Hung Kim
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