Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Patent
1999-05-10
2000-10-17
Hiteshew, Felisa
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
438706, H01L 21311
Patent
active
061331511
ABSTRACT:
A method for forming a self-aligned contact structure is disclosed based on an HDP-CVD (High-Density Plasma-Chemical Vapor Deposition) process. Initially, after a polysilicon layer and a metal layer are deposited and patterned on a wafer to fabricate a gate stack, an HDP-CVD process is employed to form a deposition layer to cover the patterned layers and wafer. A building of sharp ridges occurs over the gate stack. Next, a spacer deposition layer is then conformally deposited to cover the HDP-CVD deposition layer. An anisotropically etch process is then performed to etch the spacer deposition layer, wherein at least portions of the spacer deposition layer still covers top of the gate stack. Another anisotropically etch process is then performed to form the required contacts on the wafer. Because the HDP-CVD deposition layer on the gate structure is thick enough to protect the gate stack from etching, it is unnecessary to form the cap layer as conventionally.
REFERENCES:
patent: 5686356 (1997-11-01), Jain et al.
patent: 5851900 (1998-12-01), Chu et al.
patent: 6033981 (2000-03-01), Lee et al.
patent: 6040223 (2000-03-01), Liu et al.
Chen Kin-Chan
Hiteshew Felisa
Worldwide Semiconductor Manufacturing Corp.
LandOfFree
HDP-CVD method for spacer formation does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with HDP-CVD method for spacer formation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and HDP-CVD method for spacer formation will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-468382