HDL co-simulation in a high-level modeling system

Details HDL co-simulation in a high-level modeling system HDL co-simulation in a high-level modeling system

2007-04-10

2007-04-10

Shah, Kamini (Department: 2128)

Data processing: structural design, modeling, simulation, and em

Simulating electronic device or electrical system

Circuit simulation

C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C703S013000, C703S015000, C703S017000, C703S019000

Reexamination Certificate

active

10389161

ABSTRACT:
Method and apparatus for simulating operations of a circuit design that includes high-level components and HDL components. The high-level components of the design are simulated in a high-level modeling system (HLMS), and the HDL components of the design are simulated with an HDL simulator. Data values are converted from a data type of the HLMS to a logic vector compatible with the HDL simulator for each data value to be input to the HDL simulator, and a logic vector is converted from the HDL simulator to a data value of a data type compatible with the HLMS for each logic vector output from the HDL simulator. Events are scheduled for input to the HDL simulator as a function of the time of HLMS events and a maximum response time of the HDL components.

REFERENCES:
patent: 5910897 (1999-06-01), Dangelo et al.
patent: 5933356 (1999-08-01), Rostoker et al.
patent: 7110935 (2006-09-01), Hwang et al.
patent: 2002/0049576 (2002-04-01), Meyer
patent: 2003/0191615 (2003-10-01), Bailey et al.
patent: 1 059 593 (2000-12-01), None
Perakath Benjamin, Timothy O'Brien□□A Model-Based Approach for Component Simulation Development□□Proceedings of the 2000 Winter Simulation Conference, pp. 1831-1839.
Heneault et al□□A Fast Hardware Co-Specification and Co-Simulation MethodologyIntegrated in a H/S Co-Design Platform□□The 13th International Conference on Microelectronics, Rabat, Moroco, Oct. 29-31, 2001.
Robert Siegmund, Dietmar Muller□□SystemC: An Extension of SystemC for Mixed Multi-Level CommunicationModeling and Interface-Based System Design□□0-7695-0993-Feb. 2001 IEEE.
Kim et al□□Virtual Synchronization for Fast Distributed Cosimulation of Dataflow Task Graphs□□ISS'02 Oct. 2-4, 2002, Kyoto, Japan□□2002 ACM 1-58113-576-9/02/0010.
Benoit A. Gennart□□Comparative Design Calidation Based on Event Pattern Mappings□□30th ACM/IEEE Design Automation Conference□□1993 ACM 0-89791-577-1/93/0006-0373.
Serge Maginot□□Evaluation Criteria of HDLs: VHDL Compared to Verilog, UDL/I & M□□0-8186-2780-8/92 1992 IEEE.
Cary Ussery et al.; “HDL and Integrating System-Level Simulation Technologies”; IEEE 1997; pp. 91-97.
Agilent Technologies; “Advanced Design System 2002—HDL Cosimulation”; Feb. 2002; pp. 1-1 through 1-14.
Stuart Swan; “An Introduction to System Level Modeling in SystemC 2.0”; 2001 Open SystemC Initiative (OSCI); pp. 1-10.
U.S. Appl. No. 10/388,681, filed Mar. 14, 2003, Milne et al.
U.S. Appl. No. 10/388,936, filed Mar. 14, 2003, Milne et al.
U.S. Appl. No. 10/389,368, filed Mar. 14, 2003, Ma et al.
C. Valderrama et al.; “Automatic VHDL-C Interface Generation for Distribution Cosimulation: Application to Large Design Examples”; Design Automation for Embedded Systems; vol. 3, No. 2-3; Copyright 1998 Kluwer Academic Publishers; Mar. 1998; pp. 199-216.
C. A. Valderrama et al.; “Automatic Generation of Interfaces for Distributed C-VHDL Cosimulation of Embedded Systems: an Industrial Experience”: Rapid System Prototyping; Proceedings of the Seventh IEEE International Workshop on Thessaloniki, Greece; Jun. 19-21, 1996; pp. 72-77.
Jay Lawrence et al.; “INCA: A Next-Generation Architecture for Simulation”; Verilog HDL Conference Proceedings; Feb. 26-28, 1996; 1996 IEEE International; pp. 12-16.
Sungioo Yoo et al.; “A Generic Wrapper Architecture for Multi-Processor SoC Cosimulation and Design”; Proceedings of the 9th International Workshop on Hardware/Software Codesign Codes; Apr. 25-27, 2001; pp. 195-200.
Heiko Hubert; “A Survey of HW/SW Cosimulation Techniques and Tools”; Royal Institute of Technology; Jun. 1998; pp. 1-48.

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