Having halo regions integrated circuit device structure

Details Having halo regions integrated circuit device structure Having halo regions integrated circuit device structure

1991-09-30

1999-04-13

Wallace, Valencia

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257336, 257344, H01L 2976, H01L 31062, H01L 31113

Patent

active

058941584

ABSTRACT:
A mask is used for lightly doped drain and halo implants in an integrated circuit device. The mask exposes only portions of the substrate adjacent to field effect transistor gate electrodes. Since the halo implant is made only near the transistor channels, where it performs a useful function, adequate device reliability and performance is obtained. Since the halo implant is masked from those portions of the active regions for which it is not necessary, active region junction capacitances are lowered. Such lowered capacitances result in an improved transistor switching speed. The mask used to define the lightly doped drain and halo implant region can be easily formed from a straight forward combination of already existing gate and active area geometries.

REFERENCES:
patent: 4342149 (1982-08-01), Jacobs et al.
patent: 4597824 (1986-07-01), Shinada et al.
patent: 4642878 (1987-02-01), Maeda
patent: 4771014 (1988-09-01), Liou et al.
patent: 4843023 (1989-06-01), Chiu et al.
patent: 4855246 (1989-08-01), Codella et al.
patent: 4894694 (1990-01-01), Cham et al.
patent: 4950617 (1990-08-01), Kumagai et al.
patent: 4968639 (1990-11-01), Bergonzoni
patent: 5227321 (1993-07-01), Lee et al.
Ogura et al., "A Half Micron MOSFET using Double Implanted LDD" paper 29.6 from the 1982 IEDM Digest1.
Ogura et al., "A half micron MOSFET using double implanted LDD" 1982 IEDM Technical Digest pp. 718-721.
Patent Abstracts of Japan, vol. 009, No. 197 (E-335), Aug. 14, 1985 & JP-A-60 064472 (Toshiba KK), Apr. 13, 1985.
IEEE Journal of Solid-State Circuits, Apr. 1989, USA. vol. 24, No. 2, ISSN 0018-9200, pp. 380-387, XP0000050753 Liou F-T et al: A 0.8-mu m CMOS technology for high-performance ASIC memory and channelless gate array.
Patent Abstracts of Japan, vol. 010, No. 133 (E-404), May 17, 1986 & JP-A-60 263468(Toshiba KK), Dec. 26, 1985 *abstract; figure 1*.
Patent Abstracts of Japan, vol. 009, No. 277 (E-335), Nov. 6, 1985 & JP-A-60 121765 (Toshiba KK), Jun. 29, 1985 *abstract; figure 4*.
Patent Abstracts of Japan, vol. 013, No. 139 (E-738), Apr. 6, 1989 & JP-A-63 302565 (Sanyo Electric Co. Ltd), Dec. 9, 1988, *abstract; figures 1,2*.
Patent Abstracts of Japan, vol. 004, No. 189 (E-039), Dec. 25, 1980 & JP-A-55 130171 (Fujitsu Ltd), Oct. 8, 1980, *abstract; figure 3*.
Electronics Letters, Feb. 4, 1988, UK. vol. 24, No. 3, ISSN 0013-5194, pp. 146-147, XP002000188, Yoshimi M et al.; Study of the operation speed of half-micron design rule CMOS ring oscillators.
Lineback,J.Robert, "Triple Diffusion doubles RAM Speed", Electronics May 5, 1983, pp. 54, 61.

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