Hardware realized state machine

Details Hardware realized state machine Hardware realized state machine

2000-07-25

2002-01-22

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C326S046000, C709S241000, C709S241000, C711S103000

Reexamination Certificate

active

06341367

ABSTRACT:

BACKGROUND
Control functions such as state machines are typically implemented in software that controls a general-purpose microprocessor. One typical advantage of implementing control functions in software is that doing so provides flexibility to modify or alter the control functions since a programmer is able to modify and recompile the source code to implement the changes. However, software implemented state machines are typically slower than state machines that are realized directly in hardware using logic gates. A disadvantage of hardware realized state machines is that once a design has been implemented, changing the control functions of the state machine requires redesigning the hardware circuit thereby making any changes difficult or impractical. Furthermore, the performance of a state machine is reduced when it must wait for and process incoming packets of data. This slows down the performance of the state machine since the state machine must wait for a complete packet to be sent. Thus, there lies a need for a state machine design that provides improved flexibility and performance.
SUMMARY
The present invention is directed to a state machine realized in hardware that provides the flexibility of a software realized state machine while providing the performance advantage of a hardware circuit. The flexibility of the hardware realized state machine is achieved by providing the state machine with programmable registers to allow changes in the state machine to be implemented. The present invention is further directed to a state machine design in which a first state machine receives and processes incoming data packets and only provides the received packets to a second state machine when an incoming data packet has been received in its entirety, thereby freeing the second state machine to provide a higher level of performance.
A state machine is capable of providing improved performance as realized in a hardware embodiment while providing the flexibility of a software implemented state machine. The state machine is first implemented in software, and then is realized in a hardware embodiment based upon the software implemented state machine. Flexibility is added to the hardware realized state machine by providing registers for the hardware embodiment so that the register corresponds to states of the software implementation. As a result, at least one aspect of the hardware realized state machine may be modified without requiring redesigning the configuration of the hardware embodiment. The performance of the state machine is improved by providing a separate state machine for receiving incoming data packets so that a main state machine is capable of operating without interruption by the incoming data packets and is capable of receiving the incoming data packets from the separate, incoming data packet receiving state machine only when the main state machine is ready to receive the incoming information.


REFERENCES:
patent: 5227783 (1993-07-01), Shaw et al.
patent: 5463757 (1995-10-01), Fandrich et al.
patent: 5477168 (1995-12-01), Thijssen et al.
patent: 5594656 (1997-01-01), Tamisier
patent: 6154763 (2000-11-01), Thijssen

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