Hardware port scheduler (PTS) having register to indicate...

Details Hardware port scheduler (PTS) having register to indicate... Hardware port scheduler (PTS) having register to indicate...

2005-09-28

2008-11-11

Patel, Niketa I (Department: 2181)

Electrical computers and digital data processing systems: input/

Input/output data processing

Peripheral adapting

C710S001000, C710S036000, C710S305000, C710S306000, C718S102000

Reexamination Certificate

active

07451255

ABSTRACT:
According to one embodiment, an apparatus is disclosed. The apparatus includes a port having a plurality of lanes, a plurality of protocol engines. Each protocol engine is associated with one of the plurality of lanes, and processes tasks to be forwarded to a plurality of remote nodes. The apparatus also includes a first port task scheduler (PTS) to manage the tasks to be forwarded to the one or more of the plurality of protocol engines. The first PTS includes a register to indicate which of the plurality of protocol engines the first PTS is to support.

REFERENCES:
patent: 6434590 (2002-08-01), Blelloch et al.
patent: 6944155 (2005-09-01), Block et al.
patent: 2007/0073857 (2007-03-01), Chang et al.

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