Hardware mechanism for receiving frames from a link

Details Hardware mechanism for receiving frames from a link Hardware mechanism for receiving frames from a link

2007-06-12

2007-06-12

Chung, Phung My (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S749000, C714S047300

Reexamination Certificate

active

09961012

ABSTRACT:
A method and system for extensions to earlier patents dealing with the implementation of the InterSystem Channel (ISC) link architecture. First, it describes hardware state machines that handle all valid link messaging sequences without any processor involvement. These state machines also process larger commands and responses that may be divided into multiple frame segments. Finally, the missing frame detection is expanded for the multi frame segment commands and responses.

REFERENCES:
patent: 4947484 (1990-08-01), Twitty et al.
patent: 5422893 (1995-06-01), Gregg et al.
patent: 5490153 (1996-02-01), Gregg et al.
patent: 5574945 (1996-11-01), Elko et al.
patent: 5968179 (1999-10-01), Barkey et al.
patent: 2002/0038336 (2002-03-01), Abileah et al.

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