Hardware looping mechanism and method for efficient...

Details Hardware looping mechanism and method for efficient... Hardware looping mechanism and method for efficient...

2007-09-18

2007-09-18

Sparks, Donald (Department: 2181)

Electrical computers and digital processing systems: processing

Processing control

Branching

C712S233000, C712S234000

Reexamination Certificate

active

10844941

ABSTRACT:
A hardware looping mechanism and method is described herein for handling any number and/or type of discontinuity instruction that may arise when executing program instructions within a scalar or superscalar processor. For example, the hardware looping mechanism may provide zero-overhead looping for branch instructions, in addition to single loop constructs and multiple loop constructs (which may or may not be nested). Zero-overhead looping may also be provided in special cases, e.g., when servicing an interrupt or executing a branch-out-of-loop instruction. In addition to reducing the number of instructions required to execute a program, as well as the overall time and power consumed during program execution, the hardware looping mechanism described herein may be integrated within any processor architecture without modifying existing program code.

REFERENCES:
patent: 4556063 (1985-12-01), Thompson et al.
patent: 4858115 (1989-08-01), Rusterholz et al.
patent: 5524223 (1996-06-01), Lazaravich et al.
patent: 6766444 (2004-07-01), Singh et al.

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