Hardware I/O control block array for mirrored data transfers

Electrical computers and digital data processing systems: input/ – Input/output data processing – Direct memory accessing

Reexamination Certificate

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Details

C710S005000, C710S052000, C710S053000, C710S054000, C714S001000, C714S006130, C707S793000

Reexamination Certificate

active

06862631

ABSTRACT:
A single host adapter hardware I/O control block contains information used to specify a transfer of data from a host system to a first target device and in addition information that specifies whether the data is to be mirrored, and if so, optionally identifies a second target device on which the data is to be mirrored. After transferring the single hardware I/O control block to the host adapter integrated circuit, the host adapter integrated circuit determines whether the hardware I/O control block specifies a mirrored transaction. If a mirrored transaction is specified, the host adapter integrated circuit generates a second hardware I/O control block for the second target device using the information in the first hardware I/O control block. When the execution of both hardware I/O control blocks is complete, the host adapter integrated circuit provides a single completion notification to the host system.

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“Preliminary Amendment” for U.S. Patent Application entitled “A Hardware I/O Control Block Structure for Mirrored and Non-Mirrored Data Transfers,” of B. Arlen Young filed on Feb. 12, 2004 6 pages
Preliminary Amendment for U.S. Patent Application entitled “A Method for Configuring a Single Hardware I/O Control Block Architecture for Use with Both Mirrored and Non-Mirrored Data Transfers,” of B. Arlen Young filed on Feb. 12, 2004 6 pages.

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