Hardware driven processor state storage prior to entering a...

Details Hardware driven processor state storage prior to entering a... Hardware driven processor state storage prior to entering a...

2008-11-05

2011-12-27

Auve, Glenn A (Department: 2111)

Electrical computers and digital processing systems: support

Computer power control

Power conservation

C713S323000, C713S324000

Reexamination Certificate

active

08086883

ABSTRACT:
A data processing apparatus includes a processor for processing data and having memory interface logic for controlling transfer of data to a memory. Also included is a memory for storing data processed by said processor. The processor is powered in a first domain and the memory is powered in a second domain. A system bus is coupled to the processor and the memory to transfer data therebetween in response to memory transfer requests. The processor is responsive to a low power request to enter a low power mode to control transfer of state data indicating a current state of the processor to the memory via the system bus using memory interface logic. The state data is sufficient to restore the processor to an equivalent program state following exit from the low power mode, store the state data in memory; and power down the first domain.

REFERENCES:
patent: 5784628 (1998-07-01), Reneris
patent: 6968469 (2005-11-01), Fleischmann et al.
patent: 7624215 (2009-11-01), Axford et al.
patent: 7895458 (2011-02-01), Kim
patent: 2003/0101362 (2003-05-01), Dia
patent: 2 395 302 (2004-05-01), None
UK Search Report for GB Application No. 0724765.3, dated Apr. 11, 2008, (3 pages).
U.S. Appl. No. 12/010,401, Axford et al., filed Jan. 24, 2008.

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