Hardware detected command-per-clock

Details Hardware detected command-per-clock Hardware detected command-per-clock

2006-06-06

2006-06-06

Moazzami, Nasser (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

C711S154000, C345S531000, C345S566000

Reexamination Certificate

active

07058752

ABSTRACT:
A memory controller is coupled to a memory device via a memory channel. The memory controller includes a command-per-clock detection unit that compares a portion of a current address with a portion of a previous address. If there is a match, then the memory controller can continue to assert a chip select line coupled to the memory device. The command-per-clock detection unit checks to see whether only certain low-order bits of the address lines are toggling between the current and previous addresses. Additional copies of address lines for particular low-order bits are provided to the memory device to reduce loading on the low order bit address lines, allowing the low order bit address lines to toggle quickly in order to avoid the necessity of inserting a one clock period wait state. If the command-per-clock detection unit does not find a match (meaning that more than the low order address bits are toggling) then the wait state is inserted by deasserting the chip select line for a clock period.

REFERENCES:
patent: 6260121 (2001-07-01), Jeddeloh
patent: 6442645 (2002-08-01), Freker
patent: 6714463 (2004-03-01), Han et al.
Intel Corporation, “Intel® 845G/845GL/845GV Chipset: Intel® 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH)”, Product Datasheet, Document No. 290746-002, Sections 1.3, 1.4.2 and 2.2.1 (Oct. 2002).

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