Hardware design language for the design of integrated circuits

Details Hardware design language for the design of integrated circuits Hardware design language for the design of integrated circuits

1999-04-22

2002-07-16

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C703S014000

Reexamination Certificate

active

06421808

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to the automated design of electronic circuits, and in particular to the automated design of integrated circuits using a computer system.
Digital systems are highly complex. The process of digital design is difficult and error-prone. With the help of software tools like synthesizers, simulators, verifiers, floor planners/routers, schematic editors, etc., it is now possible to design multi-million gate chips. Generally, each of these tools has its specific view and model of the world. To represent designs in a way that a tool can understand and manipulate, one uses certain languages. A Hardware Description Language (HDL) is a language used to describe the behavior of hardware so that it can be processed by the supporting CAD tools.
Historically, hardware designs are entered into a computer system using hardware description languages such as VHDL or Verilog. An HDL program was regarded as a description or model of the design. It also served as a simulation harness. These HDL's are based on a powerful, “universal” simulation mechanism—event queues. Event-driven simulation is a powerful model with which digital behavior at many levels of abstraction can be simulated.
VHDL and Verilog are the most widely used languages in which designs are described, simulated, and exchanged. The powerful simulation mechanism makes the languages not only hardware description languages, but also programming languages. Designers can describe mixed levels of abstraction of circuits, as well as test harnesses (the parts of designs which do not correspond to hardware, e.g., the I/O processing code used to setup stimulus to a circuit) in the same language, enabling simulation of the entire design. Due to their versatility, these event driven simulators have become an indispensable part of current design technology.
These powerful languages, however, do have problems. At the beginning, VHDL and Verilog suffered from being without a formal model. This means that given a program, it is hard to determine the meaning of a piece of code by reading the text without running the program. Even worse, the underlying simulation model can introduce nondeterminism, which makes it hard to determine if a bad simulation trace is a false alarm due to simulator induced nondeterminism or a design bug.
Another defect of these languages comes from their strength—they are too powerful to match perfectly with hardware. One can easily use these languages to write programs which have no corresponding hardware at all. To use these languages for both simulation and hardware synthesis, one needs to build hardware extractors for HDL programs.
Fortunately, there are models and languages that can be mapped to logic. They are the finite state machines (FSMs) and the synchronous languages. The fundamental assumption in these models/languages is that statements/logic execute arbitrarily fast in one “tick” (or one clock cycle) until they reach a stable state. In fact, this condition simply requires that the logic execute sufficiently quickly that the input signals at all latches are quiescent at the time latches are updated.
The powerful algorithms in these CAD tools have automated and speeded the design process. One major limiting factor for these tools, however, is the size of the circuits they can handle. One way to get around that problem is to decompose complex designs into smaller, managable pieces so that tools can operate on sub-circuits and generate results that can be combined. One problem with these FSM-based languages is that undefined or nondeterministic behavior can result when composing two modules, even though each by itself is well-defined. The problem is due to the fact that unrestricted communication among modules is permitted.
Accordingly, one of the goals of our invention is to provide an improved technique for the design of electronic circuits, which enables them to be represented by software, permits modules to interact with each other in a completely deterministic manner, and simplifies the design of complex circuits.
SUMMARY OF THE INVENTION
We have developed a Hardware Design Language we refer to as V++ that is designed to overcome the problems of prior art automated design techniques. In particular V++ provides a mechanism for capturing the design, not modeling the design. Previous hardware description languages like VHDL or Verilog are targeted at design modeling; the design itself was represented elsewhere. V++ presents a single, well-defined, tool-neutral semantics to the user. V++ solves the problem of compositionality—two well-defined V++ parts, when combined, are well-defined. V++ makes the execution flow explicit, enabling the use of well-developed optimization techniques on larger designs.


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