Hardware data race detection in HPCS codes

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability

Reexamination Certificate

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Details

C714S012000, C711S144000, C711S147000, C711S150000

Reexamination Certificate

active

07823013

ABSTRACT:
A method and system for detecting race conditions computing systems. A parallel computing system includes multiple processor cores is coupled to memory. An application with a code sequence in which parallelism to be exploited is executed on this system. Different processor cores may operate on a given memory line concurrently. Extra bits are associated with the memory data line and are used to indicate changes to corresponding subsections of data in the memory line. A memory controller may perform a comparison between check bits of a memory line to determine if more than one processor core modified the same section of data in a cache line and a race condition has occurred.

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