Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2000-08-29
2003-10-28
Moise, Emmanuel L. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
Reexamination Certificate
active
06640320
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to circuitry for testing the contents of large capacity memory devices and the operation of electronic equipment including such devices.
BACKGROUND OF THE INVENTION
As memory devices get larger in capacity, and cheaper in price, electronic equipment is designed to make use of larger quantities of memory. For example, electronic equipment such as digital oscilloscopes and logic analyzers use memories to store test data received from units-under-test. Recently, for example, logic analyzers have been designed to include on the order of 300 to 400 megabytes, or more, of high speed (e.g. 12 nanosecond (ns)) memory. These instruments must be manufactured, tested and calibrated before being sold, all of which involve testing the memory. In addition, before each use, the instruments must be tested to ensure they are in operational order, including testing of the memory. Some of these tests test the proper operation of the memory by itself, and others use the memory to test the proper operation of other portions of the instrument.
In the former tests, data is written directly into the memory device, then the contents of the memory device are retrieved and checked to ensure that they are as desired. In the latter tests, other circuitry in the instrument is used to write data into the memory, then the contents of the memory are retrieved and checked to determine if the memory contains the expected values. For example, in a logic analyzer or oscilloscope, a probe may be connected to a source of a signal, such as an external pattern generator, which, if processed properly, would cause data having a known pattern of values to be stored in successive locations in the memory. After such a signal has been acquired, processed and stored, the memory is checked to determine of it has the expected data value pattern. Alternatively, a pattern generator may be included in the processing circuitry chain to generate data which should result in a predetermined pattern of data in the memory.
One prior art solution used a microprocessor to test the memories, or determine whether the content of the memory was as desired. The microprocessor wrote data into, and/or retrieved data from, the memory being tested and checked the retrieved data against expected values. The memory itself is very high speed (e.g. 12 ns, as described above) and capable of being completely filled and read-back in a reasonable amount of time. However, even the fastest microprocessor is much slower than that, and would take a relatively long time to test a memory as large as 20 megabytes. When such processors are used to test such large memories, the testing can require testing times on the order of hours. This is too long for manufacturing and calibration, and far too long for self-testing when a user first powers up the equipment.
Another prior art solution speeds up memory testing, compared to using a microprocessor, by using dedicated memory testing hardware. Such a solution is disclosed in U.S. Pat. No. 4,414,665, issued Nov. 8, 1983 to Kimura et al. In Kimura et al., hardware is used to test the proper operation of a memory. IC chip for pass/fail purposes in a manufacturing setting. Referring to
FIG. 1
of Kimura et al., a pattern generator
11
is used to supply both an address (terminal
12
) and data (terminal
13
) to a memory unit under test
15
. The data (
13
) from the pattern generator
11
is written into the location of the memory
15
specified by the address (
12
). Data is then read from the location in the memory
15
specified by the address (
12
), and that data supplied to a comparison circuit
19
. The pattern generator
11
also supplies the result (terminal
14
) expected from the memory
15
in response to the address (
12
) and data (
13
). The expected result (
14
) is also supplied to the comparison circuit
19
. If the data retrieved from the memory
15
matches the expected result (
14
), then the pattern generator
11
increments to the next address and the process repeats until the whole memory has been tested. If the data retrieved from the memory
15
does not match the expected result (
14
) a disagreement signal is generated for that memory
15
address and stored in a fault-address memory
17
. The contents of this fault address memory
17
are retrieved by a control section
23
and analyzed to determine the operational status of the memory
15
being tested.
The hardware solution of Kimura et al. can read and write data to and from the memory at the full speed of the memory. However, the testing circuitry disclosed is for testing memory IC chips after fabrication to determine whether they operate properly. This solution requires a pattern generator
11
which has the same number of locations as that in the memory to be test, and a substantially wider word size: each location in the pattern generator
11
stores a data word which includes the address (
12
) and data (
13
) for the memory
15
and also the expected result (
14
) from the memory. This solution is also not adapted to testing a memory in situ, i.e. as it is embodied in a piece of electronic equipment. There is also no disclosure or suggestion of the disclosed circuitry using other portions of a piece of electronic equipment to fill the memory, nor is there any suggestion to read and test the memory contents after being filled in that way to test the operation of the other portions of the electronic equipment. In addition, Kimura et al. writes into, and reads from, and tests the contents of a single memory location before moving on to the next location. Put another way, it does not write data to the whole memory then test the contents of the memory. For this reason, also, it cannot be used to test the operation of other circuitry in a piece of electronic equipment.
A memory test circuit which can operate on a memory in situ at the full speed of the memory; which does not require a large pattern generator, which can write a pattern into the complete memory then check the pattern written into the memory; which can receive memory data from other circuitry in the electronic equipment and then check that data to determine if it is as expected, is desirable.
BRIEF SUMMARY OF THE INVENTION
An electronic system includes a source of test data, which, if the test data source is operating properly, is a pattern of a limited number of data words successively repeated. A memory device is coupled to the test data source and stores the test data. A memory test circuit compares the stored test data to successively repeated pattern data words and generates a signal to indicate whether the stored test data is the same as the successively repeated pattern data words.
Such a system does not rely on a microprocessor for testing of the values in the memory device, and consequently can operate at the full speed of the memory device. Using such a system also permits testing of a memory in situ. In addition, use of a pattern consisting of a limited number of data words, which is successively repeated obviates the requirement for a large pattern generator.
REFERENCES:
patent: 5894484 (1999-04-01), Illes et al.
patent: 6256760 (2001-07-01), Carron et al.
Bucher William K.
Caracappa David N.
Chase Shelly A
Moise Emmanuel L.
Tektronix Inc.
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