Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
1999-06-30
2002-07-02
Myers, Paul R. (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S240000
Reexamination Certificate
active
06415347
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to data transfers over a SCSI bus, and in particular to generation of control signals on a SCSI bus.
2. Description of Related Art
Prior single chip parallel SCSI host adapters have included a plurality of modules and an on-chip processor that controlled operation of the modules. For example, see U.S. Pat. No. 5,659,690, entitled “Programmably Configurable Host Adapter Integrated Circuit Including a RISC Processor,” issued on Aug. 19, 1997 to Stuber et al., which is incorporated herein by reference.
A typical parallel SCSI host adapter
100
included a SCSI module
130
(FIG.
1
), a sequencer
120
, a data FIFO memory circuit
160
, a memory
140
, and a host interface module
110
that were interconnected by an internal chip I/O bus CIOBUS, which was used for control of host adapter integrated circuit
100
both by a host microprocessor
170
through a host adapter driver
165
and by sequencer
120
. The combination of host adapter driver
165
, sequencer
120
, and SCSI module
130
were used for controlling both synchronous and asynchronous transfers over SCSI bus
150
.
As is known to those of skill in the art, an attention signal must be generated and maintained during portions of the SCSI protocol. In host adapter
100
, sequencer
120
manually enabled generation of the attention signal, and manually determined when to de-assert the attention signal.
Specifically, sequencer
120
enabled a bit or bits that permitted SCSI module
130
to generate automatically the attention signal during the selection protocol. See for example, commonly assigned, U.S. Pat. No. 5,838,950, entitled “Method of Operation of a Host Adapter Integrated Circuit,” issued on Nov. 17, 1998 to B. Arlen Young et al., which is incorporated herein by reference.
Sequencer
120
in determining when to de-assert the attention signal considered many factors. Specifically, sequencer
120
made the determination based on the type of sequencer control block (SCB), i.e., either a tagged queue SCB or a non-tagged queue SCB, the SCSI bus phase, and whether negotiation for a synchronous data transfer needed to be initiated. Typically, e.g., for a high-performance SCSI target device, sequencer
120
managed the attention signal while the target device was waiting for an active acknowledge signal ACK in response to an active request signal REQ generated by the target device.
For a non-tagged queue SCB, sequencer
120
de-asserted the attention signal just before generating an active acknowledge signal ACK for the identify message. For a tagged queue SCB, sequencer
120
kept the attention signal asserted until just before an active acknowledge signal was generated for the tag message. If synchronous negotiation was required, sequencer
120
left the attention signal asserted until host adapter driver
165
de-asserted the signal during negotiation, or until the command phase was entered in which case the time for negotiation had passed. While using sequencer
120
to manage de-assertion of the attention signal provided flexibility, the management requires sequencer time, which in turn limits the response of host adapter
100
to conditions on the SCSI bus.
SUMMARY OF THE INVENTION
According to the principles of this invention, operation of a system including a parallel SCSI host adapter integrated circuit is enhanced by automatic management of the SCSI bus attention signal by hardware within the parallel SCSI host adapter integrated circuit. Unlike the prior art host adapters that required a plurality of sequencer operations to manually manage the SCSI bus attention signal, automatic hardware management of the SCSI bus attention signal (i) provides faster execution, e.g., the active acknowledge signal can be generated more rapidly than with manual control, and (ii) permits a sequencer in the host adapter integrated circuit to perform other tasks in parallel with the hardware management of the SCSI bus attention signal. Both of these factors enhance the operation of the parallel SCSI host adapter integrated circuit of this invention relative to prior art parallel SCSI host adapters.
In a parallel SCSI host adapter integrated circuit, the hardware circuit of this invention includes a SCSI bus request terminal, a SCSI bus attention terminal, and an automatic SCSI bus attention management circuit. The automatic SCSI bus attention circuit includes an automatic SCSI bus attention assertion hardware circuit coupled to the SCSI bus attention terminal and an automatic SCSI bus attention de-assertion hardware circuit coupled to the SCSI bus attention terminal and to the SCSI bus request terminal.
Upon pending initiation of a selection phase, the automatic SCSI bus attention assertion circuit asserts an active signal on the SCSI bus attention terminal. Following assertion of the active signal on the SCSI bus attention terminal, the automatic SCSI bus attention de-assertion hardware circuit counts the number of active SCSI bus request signals received from the SCSI bus request terminal.
Upon the automatic SCSI bus attention management circuit receiving a terminal count of active request signals from the SCSI bus request terminal, the automatic SCSI bus attention hardware circuit de-asserts the active signal on the SCSI bus attention terminal.
In one embodiment, the automatic SCSI bus attention de-assertion circuit includes a programmable counter. The programmable counter includes an input terminal coupled to the SCSI bus request terminal. In response to an active signal on the SCSI bus request terminal, a count of the programmable counter is changed. Upon the programmable counter counting the terminal count of active signals on the SCSI bus request terminal, the programmable counter generates an attention de-assertion signal on an output terminal of the programmable counter. In another embodiment, the input terminal of the programmable counter is a decrement terminal and the programmable counter is a decrementing counter. In yet another embodiment, the input terminal of the programmable counter is an increment terminal and the programmable counter is an incrementing counter.
According to the principles of this invention, a method for automatic hardware management of a SCSI bus attention signal in a parallel SCSI host adapter integrated circuit includes asserting automatically a SCSI bus attention signal, using a hardware circuit, upon the SCSI bus entering a selection phase, and counting active request signals received from a target device on the SCSI bus after the asserting of the SCSI bus attention signal, using a counter in the hardware circuit. Finally, the method includes de-asserting automatically the SCSI bus attention signal using the hardware circuit upon counting a terminal count of the active request signals.
The method of this invention further includes bypassing the automatic assertion and de-assertion of the attention signal. The bypassing operations can be performed either by an on-chip sequencer, or a host adapter driver for the parallel SCSI host adapter integrated circuit of this invention.
With the circuit and method of this invention, only the firmware instruction sequence required to determine the terminal count value and to load that value in the programmable counter is needed. If the on-chip sequencer determines the terminal count, the sequencer does so in the background before the selection phase.
Alternatively, a host adapter driver can derive the terminal count and pass the terminal count to the sequencer in a SCB. With the exception of moving the terminal count from the SCB to the programmable counter, management of the attention signal can be completely removed from the sequencer firmware. In either of these cases, management of the attention signal has been totally removed from firmware paths executed when a target device is connected thereby reducing the delay between receiving an active request signal from a target device and generating the host adapter's active acknowledge signal.
REFERENCES:
patent:
Adaptec, Inc.
Gunnison Forrest
Gunnison McKay & Hodgson, L.L.P.
Myers Paul R.
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