Electrical computers and digital data processing systems: input/ – Interrupt processing
Reexamination Certificate
1998-05-20
2001-06-05
Myers, Paul R. (Department: 2181)
Electrical computers and digital data processing systems: input/
Interrupt processing
C710S047000, C710S048000, C710S109000
Reexamination Certificate
active
06243785
ABSTRACT:
TECHNICAL FIELD
The present invention generally pertains to the field of computer networking. More particularly, the present invention is related to interrupt generation by a peripheral component.
BACKGROUND ART
Computers have become an integral tool used in a wide variety of different applications, such as in finance and commercial transactions, computer-aided design and manufacturing, health-care, telecommunication, education, etc. Computers are finding new applications as a result of advances in hardware technology and rapid development in software technology. Furthermore, a computer system's functionality is dramatically enhanced by coupling stand-alone computers together to form a computer network. In a computer network, users may readily exchange files, share information stored on a common database, pool resources, and communicate via e-mail and via video teleconferencing.
One popular type of computer network is known as a local area network (LAN). LANs connect multiple computers together such that the users of the computers can access the same information and share data. Typically, in order to be connected to a LAN, a general purpose computer requires an expansion board generally known as a network interface card (NIC). Essentially, the NIC works with the operating system and central processing unit (CPU) of the host computer to control the flow of information over the LAN. Some NICs may also be used to connect a computer to the Internet.
The NIC, like other hardware devices, requires a device driver which controls the physical functions of the NIC and coordinates data transfers between the NIC and the host operating system. An industry standard for interfacing between the device driver and the host operating system is known as the Network Device Interface Specification, or NDIS, which is developed by Microsoft Corporation of Redmond, Wash. The operating system layer implementing the NDIS interface is generally known as an NDIS wrapper. Functionally, the NDIS wrapper arbitrates the control of the device driver between various application programs and provides temporary storage for the data packets.
In one type of prior art system, the host operating system provides a software timer which attempts to fixedly set the rate at which the device driver will be instructed to check or “poll” the NIC to determine whether the NIC has any events to be serviced. Unfortunately, such conventional software timer approaches do not always provide for consistent and timely polling of the NIC. That is, if the operating system of the host computer is occupied with another task, the operating system can be delayed in instructing the device driver to poll the NIC. Specifically, polling of the NIC is sometimes delayed until after the operating system has completed its current task As a result, even though the software timer has been designed to have the NIC polled at a selected rate, the NIC may have wait longer than the selected time period for the polling to occur. Such an additional delay can compromise the performance characteristics of the NIC.
As yet another drawback to conventional software timer-based polling approaches, the software timer of the host operating system is typically only programmable to increments on the order of milliseconds (i.e. such prior art approaches have a “granularity” which is on the order of milliseconds). Hence, the greatest frequency with which the software timer can direct the device driver to poll the NIC is every few milliseconds. Although such a frequency may seem sufficient, under certain circumstances and in some applications, such millisecond polling frequency capability is not adequate for optimal NIC performance.
In another type of prior art system, in order for the NIC to communicate with or access the CPU, an interrupt must be generated. In such a prior art approach, hardware on the NIC generates an interrupt when the NIC has an event to be serviced. However, with the advent of high speed applications and environments such as, for example, Gigabit Ethernet or asynchronous transfer mode (ATM), data is being transferred from and arriving at the NIC at much higher rate. As a result, of the higher data transfer speeds, the generation of interrupts by the NIC becomes an increasingly critical operation parameter. In fact, conventional hardware based interrupt generation schemes could result in the NIC almost continuously asserting interrupts to the CPU of the host computer. Under such circumstances, CPU utilization becomes prohibitively excessive. That is, such prior art hardware generated interrupt approaches do not optimally minimize CPU utilization.
One conventional hardware generated interrupt approach has additional significant drawbacks associated therewith. Specifically, during typical operation, the NIC may experience periods of extremely heavy utilization (e.g. during transmission and reception of traffic bursts). Similarly, the NIC may experience periods of very light utilization (e.g. when little or no network traffic is occurring). Unfortunately, conventional hardware generated interrupt approaches, do not differentiate between periods of extremely heavy utilization and periods of very light utilization. Instead, a NIC employing such a conventional approach repeatedly generates an interrupt upon a hardware event such as, for example, receive FIFO not empty.
Thus, a need exists for a NIC which precisely and consistently generates interrupts at a predetermined frequency. A need also exists for a NIC which has the ability to generate interrupts with finer granularity than is possible with a conventional software approaches. Still another need exists for a network interface card (NIC) which meets the above-listed needs and which also generates interrupts in a manner which minimizes CPU utilization. Yet another need exists for a NIC meets the above-listed needs and which dynamically varies the frequency with which interrupts are generated.
DISCLOSURE OF THE INVENTION
The present invention provides a NIC which precisely and consistently generates interrupts at a predetermined frequency. The present invention also provides a NIC which has the ability to generate interrupts with finer granularity than is possible with a conventional software approaches. The present invention further provides a NIC which meets the above-listed needs and which also generates interrupts in a manner which minimizes CPU utilization. Additionally, the present invention provides a NIC attains the above-listed results and which dynamically varies the frequency with which interrupts are generated. The above accomplishments are achieved with a NIC having hardware-assisted, software-controlled, dynamic, interrupt generation capabilities.
Specifically, in one embodiment, the present invention uses a peripheral component driver to programmably define a duration for a time cycle of a hardware timer disposed on a peripheral component. The hardware timer is configured to cause the generation of an interrupt signal upon the expiration of the time cycle. In this embodiment, the hardware timer of the peripheral component implements the duration for the time cycle and causes the generation of an interrupt signal upon the expiration of the time cycle. In so doing, the present embodiment attains the reliability and consistency of hardware timer generated interrupts schemes, but, by controlling the hardware timer with software, the present embodiment prevents over utilization of the CPU by the hardware timer.
In another embodiment, the present invention includes the features of the above-listed embodiment and further recites having the peripheral component driver monitor activity of the peripheral component. In one such embodiment, the peripheral component driver then reprograms the duration for the time cycle of the hardware timer. The reprogramming of the time cycle of the hardware timer of the peripheral component is based upon the monitored activity of the peripheral component. In so doing the present embodiment, dynamically adjusts the frequency with which interrupts are gener
Hayek Claude
Lowe Glen H.
3Com Corporation
Myers Paul R.
Wagner , Murabito & Hao LLP
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