Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Patent
1997-10-27
2000-07-25
Wright, Norman M.
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
714 31, 714 38, G06F 1300
Patent
active
060947306
ABSTRACT:
The present invention provides a test and diagnosis system for testing an embedded processor. The test system includes an ASIC having an embedded microprocessor, a debug assist logic unit for monitoring the addresses and data from the embedded microprocessor, a debug kernel and an instruction overlay harness. When the debug assist logic block finds a predetermined set of match conditions, it interrupts the embedded microprocessor and transfers control from the code running on the microprocessor to the debug kernel. The debug kernel is coupled to the debug assist logic unit and responsive to user input, the debug kernel allows the user to trace processor transactions during code execution. A REMAP bit in the ASIC allows remapping of the microprocessor memory into a faster instruction overlay memory, allowing the code to be quickly modified during product debug.
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Jones Scott A.
Laffey Thomas M.
Lopez Ted J.
Hewlett--Packard Company
Lee Denise A.
Wright Norman M.
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