Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-10-30
2007-10-30
Do, Thuan V. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
11064727
ABSTRACT:
A hardware accelerator includes hardware support for a combinational only cycle and a latch only cycle in a simulation model with a single partition of latches and combinational logic. Preferred embodiments use a special 4-input 1-output function unit in the hardware accelerator in place of the normal latch function that write back the old latch value for combinational only cycles. Other embodiments include hardware support for separate array write disables for arrays and transparent latches depending on whether the cycle is a combinational only cycle and a latch only cycle. A conditional array write disable dependent on the occurrence of a hardware breakpoint is also included that supports switching from a latch plus combinational cycle to a latch only cycle, to give control to the user before evaluating the combinational logic if a breakpoint occurs on a latch.
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patent: 6026230 (2000-02-01), Lin et al.
patent: 2003/0171908 (2003-09-01), Schlip et al.
patent: 2004/0153302 (2004-08-01), Mukund et al.
patent: 2004/0236556 (2004-11-01), Lin
Guenther Gernot E.
Gyuris Viktor
Hoffman Harrell
Pasnik Kevin Anthony
Westermann, Jr. John Henry
Dimyan Magid Y.
Do Thuan V.
International Business Machines - Corporation
Martin Derek P.
Martin & Associates LLC
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