Hardware acceleration of high-level language code sequences...

Details Hardware acceleration of high-level language code sequences... Hardware acceleration of high-level language code sequences...

2005-09-28

2008-03-18

Do, Thuan (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

07346863

ABSTRACT:
Methods and apparatus are provided for implementing a programmable device including a processor core, a hardware accelerator, and secondary components such as memory. A designer efficiently selects one or more code sequences for acceleration. A hardware accelerator is generated with multiple master ports to allow efficient access to memory. Profiling information can be provided to allow efficient selection of code sequences.

REFERENCES:
patent: 5479355 (1995-12-01), Hyduke
patent: 5937179 (1999-08-01), Swoboda
patent: 6052773 (2000-04-01), DeHon et al.
patent: 6223274 (2001-04-01), Catthoor et al.
patent: 6282706 (2001-08-01), Chauvel et al.
patent: 6308234 (2001-10-01), Davies et al.
patent: 6339836 (2002-01-01), Eisenhofer et al.
patent: 6393433 (2002-05-01), Kalavade et al.
patent: 6421251 (2002-07-01), Lin
patent: 6466898 (2002-10-01), Chan
patent: 6467075 (2002-10-01), Sato et al.
patent: 6651225 (2003-11-01), Lin et al.
patent: 6658578 (2003-12-01), Laurenti et al.
patent: 6754763 (2004-06-01), Lin
patent: 6766460 (2004-07-01), Evoy et al.
patent: 6775763 (2004-08-01), Sexton et al.
patent: 6785873 (2004-08-01), Tseng
patent: 6810442 (2004-10-01), Lin et al.
patent: 6871341 (2005-03-01), Shyr
patent: 6877150 (2005-04-01), Miller et al.
patent: 6912706 (2005-06-01), Stamm et al.
patent: 6930689 (2005-08-01), Giacalone et al.
patent: 6952816 (2005-10-01), Gupta et al.
patent: 6993731 (2006-01-01), Whitaker et al.
patent: 7003746 (2006-02-01), Hyduke et al.
patent: 7027972 (2006-04-01), Lee
patent: 7089539 (2006-08-01), Dornan et al.
patent: 7120858 (2006-10-01), Zak et al.
patent: 7120895 (2006-10-01), Ye et al.
patent: 7162591 (2007-01-01), Miranda et al.
patent: 7185293 (2007-02-01), Ofer
patent: 7203799 (2007-04-01), Ball
patent: 2002/0133325 (2002-09-01), Hoare et al.
patent: 2002/0152060 (2002-10-01), Tseng
patent: 2002/0193893 (2002-12-01), Li et al.
patent: 2003/0093254 (2003-05-01), Frankel et al.
patent: 2003/0171908 (2003-09-01), Schilp et al.
patent: 2003/0233221 (2003-12-01), O'Brien et al.
patent: 2004/0015739 (2004-01-01), Heinkel et al.
patent: 2004/0123258 (2004-06-01), Butts
patent: 2004/0130927 (2004-07-01), Schulz et al.
patent: 2004/0194046 (2004-09-01), Singhal et al.
patent: 2005/0034002 (2005-02-01), Flautner
patent: 2005/0081170 (2005-04-01), Hyduke
patent: 2005/0228630 (2005-10-01), Tseng et al.
patent: 2005/0278680 (2005-12-01), Mukherjee et al.
Peter Clarke, “Celoxica adds simulator, debugger to Handel -C Compiler” www.EETimes.com, Jan. 30, 2001, 3 pages.
Mentor Graphics Corporation, HDL Designer Series Data sheet , www.mentor.com, May 2003, 4 pages.
Accel Chip, AccelChip Technical Overview, Accelerating the process of chip design, www.accelchip.com, Mar. 2004, 22 pages.
Peter Clarke, “Synthesis and reconfigurable startups team around Matlab”, www.EETimes.com, Aug. 20, 2002, 1 page.
Richard Goering, “Advances in system-level design roll out”, www.EETimes.com, May 19, 2003, 4 pages.
Pritchard and Wayne, Related U.S. Application entitled “Generating Components on a Programmable Device Using a High-Level Language”. U.S. Appl. No. 10/816,685, filed Apr. 1, 2004.
Pritchard and Wayne, Related U.S. Application entitled “Scheduling Logic on a Programmable Device Implemented Using a High-Level Language” U.S. Appl. No. 10/993,572, filed Nov. 16, 2004.
U.S. Appl. No. 10/816,685, Office Action dated Jun. 4, 2007.
U.S. Appl. No. 10/993,572, Office Action mailed Jan. 3, 2007.
U.S. Appl. No. 10/816,685, Office Action dated Apr. 21, 2006.
U.S. Appl. No. 10/816,685, Final Office Action dated Sep. 26, 2006.
Hauck et al., “The roles of FPGA's in reprogrammable systems”, Jan. 20, 1998 Google search.
Amira et al., “An FPGA based accelerator for discrete Hartley and fast hadamard transforms”, 2003, IEEE Int'l Midwest Symposium, vol. 2, pp. 860-863.
Wageeh et al., “FPGA based accelerator for functional simulation”, 2004, Circuits and Systems, ISCAS '04, Int'l Symposium, vol. 5, pp. 317-320.
Darte et al., “Hardware/software interface for multi-dimensional processor arrays”, 2005, IEEE Int'l Conference, pp. 28-35.
US Office Action/Final Rejection (Jul. 17, 2007) from U.S. Appl. No. 10/993,572.

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