Hardware acceleration of functional factoring

Details Hardware acceleration of functional factoring Hardware acceleration of functional factoring

2006-08-04

2009-12-29

Whitmore, Stacy A (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07640528

ABSTRACT:
A hardware accelerator factors functions during the compilation of a user design. The hardware accelerator includes cofactor units, each adapted to determine a cofactor of a function in response to a specified factorization and a set of input values. The factorization specifies the constant function inputs and varying function inputs. Each cofactor unit determines the cofactor of the function in response to a different constant value. The hardware accelerator operates all of the cofactor units simultaneously to determine some or all of the cofactors of a function for a factorization in parallel. Signature generators determine attributes of the cofactors. A signature analyzer uses these attributes to identify identical cofactors, constant cofactors, and inverse cofactors. The signature analyzer returns potentially optimal factorizations to compilation software applications for possible incorporation into user designs. The hardware accelerator may be implemented using a programmable device, such as the FPGA or other programmable device.

REFERENCES:
patent: 4631750 (1986-12-01), Gabriel et al.
patent: 4944009 (1990-07-01), Micali et al.
patent: 6912700 (2005-06-01), Franco et al.
patent: 2002/0124035 (2002-09-01), Faber et al.

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