Hardware accelerated compression

Details Hardware accelerated compression Hardware accelerated compression

2006-05-23

2006-05-23

Fleming, Fritz (Department: 2181)

Electrical computers and digital data processing systems: input/

Input/output data processing

Peripheral adapting

C710S065000, C710S066000, C709S247000

Reexamination Certificate

active

07051126

ABSTRACT:
A compression system is arranged to use software and/or hardware accelerated compression techniques to increase compression speeds and enhance overall data throughput. A logic circuit is arranged to: receive a data stream from a flow control processor, buffer the data stream, select a hardware compressor (e.g., an ASIC), and forward the data to the selected hardware compressor. Each hardware compressor performs compression on the data (e.g., LZ77), and sends the compressed data back to the logic circuit. The logic circuit receives the compressed data, converts the data to another compressed format (e.g., GZIP), and forwards the converted and compressed data back to the flow control processor. History associated with the data stream can be stored in memory by the flow control processor, or in the logic circuit.

REFERENCES:
patent: 2004/0001207 (2004-01-01), Nishimura
patent: 2004/0091042 (2004-05-01), Herath
patent: 2004/0190635 (2004-09-01), Ruehle
patent: 2004/0210668 (2004-10-01), Garakani et al.
M.J. Slattery et al., “Design Considerations for the ALDC Cores,”IBM Journal of Research and Development, Oct. 23, 1998 (5 pages).
David Mertz, “A Data Compression Primer, Theory and Strategy of Data Representation,”IBM developerWorks, May 1, 2001 (6 pages).
Nam Phamdo, “Lossless Data Compression,”Data-Compression.com, 2000-2001 (5 pages).
“LZ77 Compression,”FOLDOC, Apr. 7, 1995 (2 pages).

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