Hardmask designs for dry etching FeRAM capacitor stacks

Details Hardmask designs for dry etching FeRAM capacitor stacks Hardmask designs for dry etching FeRAM capacitor stacks

2000-12-19

2003-03-18

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S751000

Reexamination Certificate

active

06534809

ABSTRACT:

The following commonly assigned patent/patent applications are hereby incorporated herein by reference:
Pat. No./Ser. Nos.
09/739,065
09/741,650
09/702,985
09/741,675
09/741,677
09/741,688
6,211,035
09/105,738
09/238,211
FIELD OF THE INVENTION
The instant invention pertains to semiconductor device fabrication and processing and more specifically to a method of fabricating a ferroelectric memory device.
BACKGROUND OF THE INVENTION
Several trends exist, today, in the semiconductor device fabrication industry and the electronics industry. Devices are continuously getting smaller and smaller and requiring less and less power. A reason for this is that more personal devices are being fabricated which are very small and portable, thereby relying on a small battery as its only supply source. For example, cellular phones, personal computing devices, and personal sound systems are devices which are in great demand in the consumer market. In addition to being smaller and more portable, personal devices are requiring more computational power and on-chip memory. In light of all these trends, there is a need in the industry to provide a computational device which has memory and logic functions integrated onto the same semiconductor chip. Preferably, this memory will be configured such that if the battery dies, the contents of the memory will be retained. Such a memory device which retains its contents while power is not continuously applied to it is called a non-volatile memory. Examples of conventional non-volatile memory include: electrically erasable, programmable read only memory (“EEPPROM”) and FLASH EEPROM.
A ferroelectric memory (FeRAM) is a non-volatile memory which utilizes a ferroelectric material, such as strontium bismuth tantalate (SBT) or lead zirconate titanate (PZT), as a capacitor dielectric situated between a bottom electrode and a top electrode. Both read and write operations are performed for a FeRAM. The memory size and memory architecture effects the read and write access times of a FeRAM. Table 1 illustrates the differences between different memory types.
TABLE 1
FeRAM
Property
SRAM
Flash
DRAM
(Demo)
Voltage
>0.5 V
Read >0.5 V
>1 V
3.3 V
Write (12 V)
(±6 V)
Special Transistors
NO
YES
YES
NO
(High
(Low
Voltage)
Leakage)
Write Time
<10 ns
100 ms
<30 ns
60 ns
Write Endurance
>10
15
<10
5 
>10
15
>10
13
Read Time (single/
<10 ns
<30 ns
<30 ns / <2 ns
60 ns
multi bit)
Read Endurance
>10
15
>10
15
>10
15
>10
13
Added Mask for
0
~6-8
~6-8
~3
embedded
Cell Size (F~metal
~80 F
2
~8 F
2
~8 F
2
~18 F
2
pitch/2)
Architecture
NDRO
NDRO
DRO
DRO
Non volatile
NO
YES
NO
YES
Storage
I
Q
Q
P
The non-volatility of an FeRAM is due to the bistable characteristic of the ferroelectric memory cell. Two types of memory cells are used, a single capacitor memory cell and a dual capacitor memory cell. The single capacitor memory cell (referred to as a 1T/1C or 1C memory cell) requires less silicon area (thereby increasing the potential density of the memory array), but is less immune to noise and process variations. Additionally, a 1C cell requires a voltage reference for determining a stored memory state. The dual capacitor memory cell (referred to as a 2T/2C or 2C memory cell) requires more silicon area, and it stores complementary signals allowing differential sampling of the stored information. The 2C memory cell is more stable than a 1C memory cell.
In a 1T/1C FeRAM cell there is one transistor and one storage capacitor. The bottom electrode of the storage capacitor is connected to the drain of the transistor. The 1T/1C cell is read from by applying a signal to the gate of the transistor (wordline) thereby connecting the bottom electrode of the capacitor to the source of the transistor (bitline). A pulse signal is then applied to the top electrode contact (plate line or drive line). The potential on the bitline of the transistor is, therefore, the capacitor charge divided by the bitline capacitance. Since the capacitor charge is dependent upon the bistable polarization state of the ferroelectric material, the bitline potential can have two distinct values. A sense amplifier is connected to the bitline and detects the voltage associated with a logic value of either 1 or 0. Frequently the sense amplifier reference voltage is a ferroelectric or non-ferroelectric capacitor connected to another bitline that is not being read. In this manner, the memory cell data is retrieved.
A characteristic of a ferroelectric memory is that a read operation is destructive in some applications. The data in a memory cell must be rewritten back to the memory cell after the read operation is completed. If the polarization of the ferroelectric is switched, the read operation is destructive and the sense amplifier must rewrite (onto that cell) the correct polarization value as the bit just read from the cell. This is similar to the operation of a DRAM. If the drive line voltage was-small enough not to switch the ferroelectric then the read operation was not destructive. In general a non-destructive read requires a much larger capacitor than a destructive read and, therefore, requires a larger cell size.
A 2T/2C memory cell in a memory array couples to a bit line (“bitline”) and the inverse of the bit line (“bitline-bar”) that is common to many other memory types (for example, static random access memories). Memory cells of a memory block are formed in memory rows and memory columns. The dual capacitor ferroelectric memory cell comprises two transistors and two ferroelectric capacitors. A first transistor couples between the bitline and a first capacitor. A second transistor couples between the bitline-bar and a second capacitor. The first and second capacitors have a common terminal or plate to which a signal is applied for polarizing the capacitors.
In a write operation, the first and second transistors of the dual capacitor ferroelectric memory cell are enabled to couple the capacitors to the complementary logic levels on the bitline and the bitline-bar line corresponding to a logic state to be stored in memory. The common terminal of the capacitors is pulsed during a write operation to polarize the dual capacitor memory cell to one of the two logic states.
In a read operation, the first and second transistors of the dual capacitor memory cell are enabled to couple the information stored on the first and second capacitors to the bitline and the bitline-bar line. A differential signal is generated across the bitline and the bitline-bar line by the dual capacitor memory cell. The differential signal is sensed by a sense amplifier which provides a signal corresponding to the logic level stored in memory.
A memory cell of a ferroelectric memory is limited to a finite number of read and write operations before the memory cell becomes unreliable. The number of operations that can be performed on a FeRAM memory is known as the endurance of a memory. The endurance is an important factor in many applications that require a nonvolatile memory. Other factors such as memory size, memory speed, and power dissipation also play a role in determining if a ferroelectric memory is viable in the memory market.
Several requirements either presently exist or may become requirements for the integration of FeRAM with other device types. One such requirement involves utilizing, as much as possible, the conventional front end and backend processing techniques used for fabricating the various logic and analog devices on the chip to fabricate this chip which will include FeRAM devices. In other words, it is beneficial to utilize as much of the process flow for fabricating these standard logic devices (in addition to I/O devices and potentially analog devices) as possible, so as not to greatly disturb the process flow (thus increase the process cost and complexity) merely to integrate the FeRAM devices onto the chip.
It has been proposed to place the FeRAM process module at various locations of the process flow. For example, if the FeRAM process module is placed over the first l

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