Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2006-03-15
2010-02-16
Coleman, W. David (Department: 2813)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S736000, C257SE21035
Reexamination Certificate
active
07662721
ABSTRACT:
A hard mask layer stack for patterning a layer to be patterned includes a carbon layer disposed on top of the layer to be patterned, a first layer of a material selected from the group of SiO2and SiON disposed on top of the carbon layer and a silicon layer disposed on top of the first layer. A method of patterning a layer to be patterned includes providing the above described hard mask layer stack on the layer to be patterned and patterning the silicon hard mask layer in accordance with a pattern to be formed in the layer that has to be patterned.
REFERENCES:
patent: 6168904 (2001-01-01), Cuthbert et al.
patent: 7071085 (2006-07-01), Lukanc et al.
patent: 7109101 (2006-09-01), Wright et al.
patent: 7115525 (2006-10-01), Abatchev et al.
patent: 7151040 (2006-12-01), Tran et al.
patent: 7223525 (2007-05-01), Lipinski
patent: 7253118 (2007-08-01), Tran et al.
patent: 7390746 (2008-06-01), Bai et al.
patent: 2006/0077702 (2006-04-01), Sugimae et al.
patent: 10349764 (2005-06-01), None
patent: 2005076337 (2005-08-01), None
patent: 2006101695 (2006-09-01), None
Boubekeur Hocine
Caspary Dirk
Manger Dirk
Markert Matthias
Nagel Nicolas
Coleman W. David
Dicke Billig & Czaja, PLLC
Infineon - Technologies AG
Kim Sun M
LandOfFree
Hard mask layer stack and a method of patterning does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Hard mask layer stack and a method of patterning, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Hard mask layer stack and a method of patterning will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4168408