Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2000-06-20
2002-01-15
Pham, Long (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S584000, C438S197000, C438S595000
Reexamination Certificate
active
06339017
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to an integrated circuit (IC) and the fabrication of an integrated circuit. More particularly, the present invention relates to an integrated circuit and a method of making an integrated circuit having small structures or patterns.
BACKGROUND OF THE INVENTION
Ultra-large-scale integrated (ULSI) circuits generally include a multitude of transistors, such as, more than one million transistors and even several million transistors that cooperate to perform various functions for an electronic component. The transistors are generally complementary metal oxide semiconductor field effect transistors (CMOSFETs) which include a gate conductor disposed between a source region and a drain region. The gate conductor is provided over a thin gate oxide material. The gate conductor can be a metal, a polysilicon, or polysilicon/germanium (Si
x
Ge
(1−x)
) material that controls charge carriers in a channel region between the drain and the source to turn the transistor on and off. The transistors can be N-channel MOSFETs or P-channel MOSFETs.
Generally, it is desirous to manufacture smaller transistors to increase the component density on an integrated circuit. It is also desirous to reduce the size of integrated circuit structures, such as vias, contacts, conductive lines, capacitors/resistors, structures, solutions, interconnects, etc.
Lithographic tools are utilized to form transistors and other structures on the integrated circuit. As transistors and other integrated circuit structures are reduced in size (CMOS scaling), the demands on lithographic tools have increased. For example, lithographic tools can be utilized to define gate conductors, conductive lines, vias, doped regions, and other structures associated with an integrated circuit.
In one type of conventional lithographic fabrication process, a photoresist mask is coated over a substrate or a layer above the substrate. The photoresist mask is lithographically patterned by providing electromagnetic radiation, such as, ultraviolet light, through an overlay mask. The portions of the photoresist mask exposed to the electromagnetic radiation react (e.g. are cured). The unreacted portion of the photoresist mask is removed from the substrate or layer, and the pattern associated with the overlay is transposed to the photoresist mask.
The patterned photoresist mask is utilized to etch other mask layers or structures. These mask layers include hard mask layers. The etched mask layers and structures can be used to define doping regions, trenches, vias, lines, etc. Most conventional lithographic fabrication processes have only been able to define structures or regions having a minimum topographic dimension of 100 nanometers (nm) or greater.
As requirements for the size of structures or features on the integrated circuit reach levels below 100 nm or 50 nm, lithographic techniques are unable to precisely and accurately define the feature. For example, it is desirous to reduce the width of the gate conductor (the gate length) associated with a transistor. Future designs of transistors may require that the gate conductor have a width of less than 50 nm. In another example, it is desirous to create contacts or vias having a dimension of less than 50 nm.
Thus, there is a need for an integrated circuit or electronic device that includes transistors having smaller feature sizes. Further still, there is a need for ULSI circuits which do not utilize conventional lithographic techniques to define geometry. Even further still, there is a need for a non-lithographic approach for defining contacts, gates, or other integrated circuit structures having at least one topographic dimension less than 100 nanometers and even less than 50 nanometers.
SUMMARY OF THE INVENTION
An exemplary embodiment relates to a method of manufacturing a small structure on an ultra-large scale integrated circuit. The small structure has a dimension smaller than one lithographic feature. The method includes steps of lithographically patterning a mask layer above a substrate to have a mask feature, oxidizing sidewalls of the mask feature to form at least one oxidized sidewall, removing the oxidized sidewall, and etching the material in accordance with the mask feature without the at least one oxidized sidewall. The mask feature has a dimension which is one lithographic feature wide. The small structure remains after the etching step.
Another embodiment relates to a process of forming a gate conductor having a dimension less than one lithographic feature. The process includes providing a mask layer above a conductive layer above a top surface of a substrate, patterning the mask layer, oxidizing the mask layer, removing oxide sidewalls associated with the mask layer, and etching the conductive layer. The conductive layer is etched in accordance with the mask layer without the oxidized sidewalls to form the gate conductor.
Still another exemplary embodiment relates to a method of manufacturing an integrated circuit including a conductive via. The conductive via has a dimension less than one lithographic feature. The method includes providing a mask layer above a conductive material above a semiconductor substrate, patterning the mask layer to leave a structure, oxidizing sidewalls of the structure, removing the oxidized sidewalls of the structure, and etching the conductive material. The conductive material is etched in accordance with the structure without the oxidized sidewalls to form the conductive via.
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patent: 6133129 (2000-10-01), Xiang et al.
Yu, Bin, et al. “Ultra-Thin-Body Silicon-On-Insulator MOSFET's for Terabit-Scale Integration” Department of Electrical Engineering & Computer Sciences, University of California, Berkeley.
Huang, Xuejue, et al. “Sub 50-nm Fin FET: PMOS” Department of Electrical Engineering & Computer Sciences, University of California, Berkeley, 1999 IEEE.
Advanced Micro Devices , Inc.
Foley & Lardner
Pham Long
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