Hard mask etch for gate polyetch

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation

Reexamination Certificate

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Details

C438S721000, C438S791000, C438S952000, C257SE21206, C257SE21029, C257SE21038

Reexamination Certificate

active

10157192

ABSTRACT:
A transistor gate structure that is free from notches is formed by using a hard mask. The hard mask has a bilayer structure of a BARC (bottom antireflective coating) over a silicon dioxide layer. A photoresist layer is formed over a portion corresponding to the gates. A first etch forms the gate structure. Following removal of the photoresist, a second etch completely removes the BARC. The silicon dioxide layer can be removed by a subsequent wet etch with HF.

REFERENCES:
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patent: 6083852 (2000-07-01), Cheung et al.
patent: 6136679 (2000-10-01), Yu et al.
patent: 6174818 (2001-01-01), Tao et al.
patent: 6355546 (2002-03-01), Huang et al.
patent: 6670277 (2003-12-01), Sayama et al.
patent: 2000-100965 (2000-04-01), None

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