Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2007-01-16
2007-01-16
Lindsay, Jr., Walter (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S721000, C438S791000, C438S952000, C257SE21206, C257SE21029, C257SE21038
Reexamination Certificate
active
10157192
ABSTRACT:
A transistor gate structure that is free from notches is formed by using a hard mask. The hard mask has a bilayer structure of a BARC (bottom antireflective coating) over a silicon dioxide layer. A photoresist layer is formed over a portion corresponding to the gates. A first etch forms the gate structure. Following removal of the photoresist, a second etch completely removes the BARC. The silicon dioxide layer can be removed by a subsequent wet etch with HF.
REFERENCES:
patent: 5891784 (1999-04-01), Cheung et al.
patent: 6083852 (2000-07-01), Cheung et al.
patent: 6136679 (2000-10-01), Yu et al.
patent: 6174818 (2001-01-01), Tao et al.
patent: 6355546 (2002-03-01), Huang et al.
patent: 6670277 (2003-12-01), Sayama et al.
patent: 2000-100965 (2000-04-01), None
Birch & Stewart Kolasch & Birch, LLP
Lindsay, Jr. Walter
Pompey Ron
Sharp Kabushiki Kaisha
LandOfFree
Hard mask etch for gate polyetch does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Hard mask etch for gate polyetch, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Hard mask etch for gate polyetch will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3772967