Hard-decision iteration decoding based on an...

Details Hard-decision iteration decoding based on an... Hard-decision iteration decoding based on an...

2006-04-28

2009-11-10

Baderman, Scott T (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S784000, C714S792000

Reexamination Certificate

active

07617435

ABSTRACT:
A decoding system decodes forward error correction (FEC) encoded data. Factor graph circuitry (such as trellis decoder circuitry) processes the FEC encoded data according to at least one factor graph. Order restoring circuitry (such as convolutional deinterleaver circuitry) is coupled to an output of the factor graph circuitry and restores ordering of symbols in the encoded data. Error detection and correction circuitry is coupled to an output of the order restoring circuitry and processes block-based error correcting codes to detect and correct errors in the FEC encoded data and to provide a hard-decision output to an output of the decoding system. Feedback circuitry (such as convolutional interleaver circuitry and symbol interleaver circuitry) is coupled to process the hard-decision output from the error correction and detection circuitry and to provide the processed hard-decision output to the factor graph circuitry.

REFERENCES:
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patent: 6034996 (2000-03-01), Herzberg
patent: 6634007 (2003-10-01), Koetter et al.
patent: 7000174 (2006-02-01), Mantha et al.

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