Handshake minimizing serial-to-parallel interface with shift reg

Details Handshake minimizing serial-to-parallel interface with shift reg Handshake minimizing serial-to-parallel interface with shift reg

1998-06-15

2000-09-19

Kim, Kenneth S.

Electrical computers and digital data processing systems: input/

Input/output data processing

Peripheral adapting

341100, G06F 1338

Patent

active

061226831

ABSTRACT:
A serial/parallel interface for interfacing the serial port of a microcontroller with parallel bus devices, and a protocol for communicating with the same. The interface operates to maximize through-put with minimum handshaking by incorporating logic within the interface itself to control data flow. A row/column count state machine in the interface accumulates serial clock pulses from the microcontroller and controls the latching of parallel output data. A read/write state machine accumulates addresses and controls the read/write operation in response to a command sent by the microcontroller in the serial data stream. The read/write state machine accumulates addresses in response to an interface clock derived from the serial clock from the microcontroller.

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