Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-03-06
2007-03-06
Lin, Sun James (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
10847692
ABSTRACT:
A method and system is provided for handling unused structures in a slice during custom instance creation to avoid the need of a boundary scan synthesis tool, wherein the slice includes an embedded boundary scan chain having a particular length and order. Aspects of the present invention include using a software tool during slice creation to create at least one slice connectivity file. During instance creation, a customer designs a custom chip using the software tool by selecting which structures are to be use on the slice. The slice connectivity file is then reused for the instance by reading the connectivity file to determine which structures in the file are used and not used based on the customer's selections. Thereafter, the slice is reconfigured to include dummy logic in unused structures, such that the boundary scan chain retains the same length and order.
REFERENCES:
patent: 5682392 (1997-10-01), Raymond et al.
patent: 5761215 (1998-06-01), McCarthy et al.
patent: 6427217 (2002-07-01), Hartnett
patent: 6973608 (2005-12-01), Abramovici et al.
patent: 2002/0083387 (2002-06-01), Miner et al.
patent: 2005/0039089 (2005-02-01), Gedamu et al.
Lin Sun James
LSI Logic Corporation
Strategic Patent Group Inc.
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