Handling multiple delayed write transactions simultaneously...

Details Handling multiple delayed write transactions simultaneously... Handling multiple delayed write transactions simultaneously...

1999-06-08

2002-08-27

Wong, Peter (Department: 2181)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S310000

Reexamination Certificate

active

06442641

ABSTRACT:

This invention is generally related to bridges used for communication between separate buses, and more particularly to simultaneously handling multiple delayed write transactions through a bridge.
BACKGROUND INFORMATION
The performance of electronic systems can be enhanced through the use of multiple buses that allow a larger number of devices to become part of the system. Devices on one bus communicate with devices on a physically separate bus through a bridge. Transactions across the bridge are requested by an initiator coupled to an initiating bus, and are directed at a target coupled to a target bus on the other side of the bridge. Transaction data being transferred between the initiator and the target is received one portion at a time by the bridge and stored in a buffer before being forwarded to the other side of the bridge.
One type of transaction that is particularly common in such systems is the delayed write transaction. Such a transaction may be one which complies with the popular Peripheral Component Interconnect (PCI) Specification, Rev. 2.1, Jun. 1, 1995. Typically, after an initial PCI delayed write transaction is requested on the initiating bus, the bridge claims the transaction by latching address and command type information associated with this initial request. In addition, the bridge will capture a predefined amount of data, such as a single data word, and then terminates the transaction by signaling a retry termination in response to the request. The retry termination indicates to the initiator that the transaction has not been completed. Meanwhile, the bridge initiates a transaction on the target bus in an attempt to transfer the buffered data to the target. When the target becomes available, the bridge transfers the portion of data from its buffer to the target and the transaction is deemed completed on the target bus. Thereafter, if the initiator returns and repeats the initial transaction request, the bridge once again accepts an initial portion of data from the initiator, but this time signals a successful, rather than a retry, termination in response to the repeated request. This successful termination signifies to the initiator that its transaction has been completed.
In conventional PCI bridges, a delayed write transaction must be completed on the initiating bus before subsequent delayed write transactions can be accepted in the same direction across the bridge. Such a solution, however, creates a performance bottleneck in systems with relatively high bridge traffic, such as network servers.
SUMMARY
Accordingly, an embodiment of the invention is directed at a method of processing multiple delayed write transactions by a bridge. The method involves receiving a number of requests for delayed write transactions on an initiating side of the bridge, and storing received transaction information for each of the requests in a separate one of a number of storage elements. An element containing newly received transaction information is marked valid if no received transaction information in other elements matches the newly received transaction information. Then, a delayed write transaction corresponding to the valid element is mastered on a target side of the bridge. If the corresponding delayed write transaction is completed on the target side, then the valid element is marked as complete. Thereafter, a new request received on the initiating side is signaled a successful termination if received transaction information for the new request matches that stored in the valid and complete element.


REFERENCES:
patent: 5815677 (1998-09-01), Goodrum
patent: 5832241 (1998-11-01), Guy et al.
patent: 5832243 (1998-11-01), Seeman
patent: 6219737 (2001-04-01), Chen et al.
patent: 6230219 (2001-05-01), Fields, Jr. et al.
patent: 6230228 (2001-05-01), Eskandari et al.
patent: 6260095 (2001-07-01), Goodrum

Affiliated with

Also associated with

Rating

Handling multiple delayed write transactions simultaneously... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Handling multiple delayed write transactions simultaneously..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Handling multiple delayed write transactions simultaneously... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2920203