Handling multiple data transfer requests within a computer...

Details Handling multiple data transfer requests within a computer... Handling multiple data transfer requests within a computer...

2006-09-20

2008-12-23

Patel, Niketa I (Department: 2181)

Electrical computers and digital data processing systems: input/

Input/output data processing

Direct memory accessing

C710S036000, C710S039000, C710S042000

Reexamination Certificate

active

07469305

ABSTRACT:
In response to multiple data transfer requests from an application, a data definition (DD) chain is generated. The DD chain is divided into multiple DD sub-blocks by determining a bandwidth of channels (BOC) and whether the BOC is less than the DD chain. If so, the DD chain is divided by the available DMA engines. If not, the DD chain is divided by an optimum atomic transfer unit (OATU). If the division yields a remainder, the remainder is added to a last DD sub-block. If the remainder is less than a predetermined value, the size of the last DD sub-block is set to the OATU plus the remainder. Otherwise, the size of the last DD sub-block is set to the remainder. The DD sub-blocks are subsequently loaded into a set of available DMA engines. Each of the available DMA engines performs data transfers on a corresponding DD sub-block until the entire DD chain has been completed.

REFERENCES:
patent: 6721826 (2004-04-01), Hoglund
patent: 6839824 (2005-01-01), Camble et al.
patent: 6999999 (2006-02-01), Camble et al.
patent: 7287114 (2007-10-01), Sullivan
patent: 2005/0025119 (2005-02-01), Pettey et al.
patent: 2006/0015473 (2006-01-01), Swan

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