Handling fetch requests that return out-of-order at an...

Details Handling fetch requests that return out-of-order at an... Handling fetch requests that return out-of-order at an...

2006-07-24

2010-02-16

Bragdon, Reginald G (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S118000

Reexamination Certificate

active

07664918

ABSTRACT:
One embodiment of the present invention provides a system that handles instruction fetch requests that return out-of-order at an IFU of a processor. During operation, the system sends a request to obtain a cache line to an instruction cache, wherein the request can be serviced and the cache line can be sent to a fetch buffer before a preceding cache line for a preceding request has returned from the instruction cache. In response to the request, the system receives the cache line from the instruction cache. Next, the system determines whether the cache line was returned out-of-order with respect to the preceding cache line. If so, the system performs an action to handle the out-of-order return.

REFERENCES:
patent: 5761713 (1998-06-01), Lesartre
patent: 6594755 (2003-07-01), Nuechterlein et al.
patent: 6895475 (2005-05-01), Volpe et al.
patent: 6938146 (2005-08-01), Shafi et al.

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