Electrical computers and digital processing systems: processing – Processing control – Branching
Reexamination Certificate
1998-08-31
2001-10-16
Maung, Zarni (Department: 2154)
Electrical computers and digital processing systems: processing
Processing control
Branching
Reexamination Certificate
active
06304963
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the handling of exceptions in data processing apparatus. More particularly, this invention relates to a data processing apparatus and method for handling exceptions occurring during processing of vector instructions.
2. Description of the Prior Art
It is known to provide data processing systems that support vector instructions. Examples of such systems are the Cray 1 and Digital Equipment Corporation MultiTitan processors.
Vector instructions are desirable as they allow code density to be increased since a single instruction can specify a plurality of data processing operations. Digital signal processing such as audio or graphics processing is particularly well suited to exploiting vector operations as there is often a requirement to perform the same operation upon a sequence of related data values, e.g. performing a filter operation by multiplying a sequence of signal values by tap coefficients of a digital filter.
Typically, the data processing system is arranged to have a number of registers for storing data values required for execution of the data processing operations specified by the vector instruction. The vector instruction is then decoded into N scalar data processing operations (where N represents the vector length), typically taking the form of N iterations of a particular data processing operation, each iteration operating on a different set of register numbers.
It is proposed to provide a data processing apparatus for processing vector instructions, whereby a vector instruction is decoded into a sequence of data processing operations, and an execution unit comprising a plurality of pipelined stages is then provided for executing the sequence of data processing operations. Each data processing operation is passed one after the other through the execution unit. Such an approach enables vector processing to be achieved in a data processing apparatus which is smaller, consumes less power, and is cheaper, than conventional vector machines which execute the constituent data processing operations of a vector instruction in parallel.
One problem that arises when processing vector instructions in a data processing apparatus that employs an execution unit comprising a plurality of pipelined stages is that of handling exceptions that may occur during the processing of the vector instruction. Any of the scalar iterations in to which the vector operation is decomposed could give rise to an exception condition being detected. In such a situation, provision needs to be made for handling such an exception condition when it arises, in order to ensure that the vector instruction is processed correctly.
One way to achieve this is to pass the entire vector instruction to an exception processing tool for handling. Whilst this ensures that an effective procedure is in place for handling an exception occurring during processing of a vector instruction, it effectively means that any time spent by the data processing apparatus in processing scalar iterations of the vector instruction prior to detection of the exception condition is wasted.
It is an object of the present invention to provide an improved technique for handling exceptions occurring during processing of vector instructions.
SUMMARY OF THE INVENTION
Viewed from the first aspect, the present invention provides a data processing apparatus comprising: an instruction decoder for decoding a vector instruction representing a sequence of data processing operations; an execution unit comprising a plurality of pipelined stages for executing said sequence of data processing operations; the execution unit including exception determination logic for determining, as each data processing operation enters a predetermined pipelined stage, whether that data processing operation is an exceptional operation matching predetermined exception criteria, the execution unit being arranged to halt processing of said exceptional operation; and an exception register for storing exception attributes relating to said exceptional operation, said exception attributes indicating which data processing operation in said sequence has been determined to be said exceptional operation; whereby the exception attributes stored in the exception register can be provided to an exception processing tool for use in handling said exceptional operation.
In accordance with the present invention, exception determination logic is provided for determining, as each data processing operation enters a predetermined pipelined stage of the execution unit, whether that data processing operation is an exceptional operation matching predetermined exception criteria. The predetermined exception criteria can be chosen dependent on the types of exceptions that the exception determination logic is looking for. Further, the predetermined exception criteria can be chosen so that the exception determination logic not only identifies data processing operations that will definitely give rise to an exception condition, but also those data processing operations that potentially may give rise to an exception condition.
For example, a data processing operation involving a divide-by-zero computation will always give rise to an exception being detected. Further, exception conditions such as overflow and underflow can be detected pessimistically by reviewing the exponents of the data values to which the data processing operation is applied. If these indicate that an exception may occur, the exception determination logic preferably identifies the data processing operation as an exceptional operation. This approach allows for rapid (single stage) and early detection of potential exceptional conditions.
When the exception determination logic identifies an exceptional operation, then in accordance with the present invention the execution unit is arranged to halt processing of the exceptional operation. Further, exception attributes relating to the exceptional operation are stored in an exception register, these exception attributes indicating which data processing operation in said sequence has been determined to be said exceptional operation. By storing such exception attributes in the exception register, it is possible for an exception processing tool to be used to handle the specific exceptional operation that has given rise to the exception condition, rather than providing the entire vector instruction for handling by the exception processing tool.
Typically, the data processing apparatus will be provided with a register bank having a plurality of registers for storing data values required for execution of said sequence of data processing operations derived from the vector instruction. Since the data processing apparatus of the present invention does not require the whole vector instruction to be handled by an exception processing tool in the event of an exception being detected, it is possible for the registers associated with a particular data processing operation in the sequence to be quickly released for use by subsequent instructions, rather than having to ensure that those registers are “locked” until the entire vector instruction has completed. For example, in preferred embodiments, the source registers are released as soon as the data values in those registers have been read. Hence, the present invention allows reduced resource locking to be accommodated.
In preferred embodiments, the data processing apparatus further comprises a register bank having a plurality of registers for storing data values used for said sequence of data processing operations, said exception attributes including first data identifying the registers containing the data values to be used for the exceptional operation. By this approach, the speed of operation of the exception processing tool can be improved, since the exception processing tool is provided directly with the registers containing the data values required to handle the exceptional operation, rather than having to derive those registers separately, as would be required if the exc
ARM Limited
Chang Jung-won
Maung Zarni
Nixon & Vanderhye P.C.
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