Handling data cache misses out-of-order for asynchronous...

Electrical computers and digital processing systems: processing – Processing control

Reexamination Certificate

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C712S225000

Reexamination Certificate

active

07900024

ABSTRACT:
Mechanisms for handling data cache misses out-of-order for asynchronous pipelines are provided. The mechanisms associate load tag (LTAG) identifiers with the load instructions and uses them to track the load instruction across multiple pipelines as an index into a load table data structure of a load target buffer. The load table is used to manage cache “hits” and “misses” and to aid in the recycling of data from the L2 cache. With cache misses, the LTAG indexed load table permits load data to recycle from the L2 cache in any order. When the load instruction issues and sees its corresponding entry in the load table marked as a “miss,” the effects of issuance of the load instruction are canceled and the load instruction is stored in the load table for future reissuing to the instruction pipeline when the required data is recycled.

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Martinez, Jose F., et al., Cherry: Checkpointed Early Resource Recycling in Out-of-order Microprocessors, 2002, IEEE, pp. 3-14.

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