Half-rate clock logic block and method for forming same

Details Half-rate clock logic block and method for forming same Half-rate clock logic block and method for forming same

2005-03-15

2005-03-15

Cho, James H. (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Sequential or with flip-flop

C326S093000

Reexamination Certificate

active

06867617

ABSTRACT:
A method and apparatus for converting a full-rate digital clock circuit to a fractional-rate clock circuit. The combinatorial and sequential functions of the full rate design are duplicated, with a first combinatorial function responsive to even input logic vectors and a second combinatorial function responsive to odd input logic vectors. Output vectors from the first and the second combinatorial function are provided as input vectors to the respective first and second sequential function, which operate at a fractional clock rate and provide the output block vectors.

REFERENCES:
patent: 5301196 (1994-04-01), Ewen et al.
patent: 5440245 (1995-08-01), Galbraith et al.
patent: 6133758 (2000-10-01), Durham et al.
patent: 6515504 (2003-02-01), Carro

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