Static information storage and retrieval – Read/write circuit – Separate read and write bus
Reexamination Certificate
2003-01-21
2004-08-24
Tran, M. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Separate read and write bus
C365S226000
Reexamination Certificate
active
06781891
ABSTRACT:
This application claims priority from Korean Priority Document No. 2002-3324, filed on Jan. 21, 2002, which is hereby incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a voltage generator. More particularly, the present invention relates to a half power supply voltage generator and a semiconductor memory device having the same.
2. Description of Related Art
A typical half power supply voltage generating circuit feeds back an output voltage to PMOS and NMOS transistors. The half power supply voltage generating circuit can output a stabilized half power supply voltage because resistance in the PMOS and NMOS transistors vary responsive to the feedback output voltage.
FIG. 1
is a circuit diagram of a half power supply voltage generating circuit comprised of PMOS transistors P
1
, P
2
, and P
3
and NMOS transistors N
1
, N
2
, and N
3
. Referring to
FIG. 1
, the PMOS transistor P
1
, the NMOS transistor N
1
, the PMOS transistor P
2
, and the NMOS transistor N
2
are serially connected between the power supply voltage terminal Vcc and ground voltage terminal. The NMOS transistor N
3
and the PMOS transistor P
3
are serially connected between the power supply voltage terminal Vcc and the ground voltage terminal. The PMOS transistor P
1
comprises a source for receiving a power supply voltage Vcc, a gate connected to a node B and a drain connected to a node C. The NMOS transistor N
1
comprises a drain and a gate commonly connected to node C, and a source connected to node A. The PMOS transistor P
2
comprises a source connected to node A, and a gate, and a drain commonly connected to a node D. The NMOS transistor N
2
comprises a drain connected to node D, a gate connected to node B and a source for receiving the ground voltage. The NMOS transistor N
3
comprises a drain for receiving the power supply voltage Vcc, a gate connected to node C, and a source connected to the node B. The PMOS transistor P
3
comprises a source connected to node B, a gate connected to node D, and a drain for receiving the ground voltage is applied. A substrate on which the PMOS transistors P
1
and P
3
are formed is connected to a bulk supply voltage. A substrate on which the PMOS transistor P
2
is formed is connected to the substrate of the PMOS transistors P
1
and P
3
. A substrate on which the NMOS transistors N
1
, N
2
, N
3
are formed is connected to the bulk supply voltage.
The circuit of
FIG. 1
operates as follows. The output voltage VOUT is half of the power supply voltage Vcc (node A is designed to be ½ Vcc). A voltage at node C becomes ½ Vcc+VTN. A voltage at node D becomes ½ Vcc−VTP. VTP is a threshold voltage of the PMOS transistor P
2
and VTN is a threshold voltage of the NMOS transistor N
1
. Accordingly, the NMOS transistor N
3
and the PMOS transistor P
3
are both slightly turned on, thereby generating a stable output voltage VOUT with half power supply voltage. When output voltage VOUT decreases, the resistance of the PMOS transistor P
1
decreases while the resistance of the NMOS transistor N
2
increases, thereby raising a voltage at node A. The voltage at node C increases and the voltage at node D decreases as a result, so that the NMOS transistor N
3
is turned on and the PMOS transistor P
3
is turned off, thereby raising the voltage at node B.
On the other hand, when output voltage VOUT increases, the resistance of the NMOS transistor N
2
decreases and the resistance of the PMOS transistor P
1
increases, thereby decreasing the voltage at node A. Then, the voltage at node C decreases and the voltage at the node D increases, so that the PMOS transistor P
3
is turned on and the NMOS transistor N
3
is turned off, thereby decreasing the voltage at node B.
When the output voltage VOUT decreases to a level below the threshold voltages of the PMOS transistor P
1
and/or the NMOS transistor N
2
, the PMOS transistor P
1
and/or the NMOS transistor N
2
turns off, making inoperable the half power supply voltage generating circuit.
This problem is particularly relevant when a low supply voltage Vcc is applied to the circuit of
FIG. 1
because the threshold voltages of the transistors are not reduced in proportion to the supply voltage Vcc.
In general, the threshold voltage of the PMOS transistor P
1
is greater than the threshold voltage of the NMOS transistor N
2
, so that the operation of the half power supply voltage generating circuit depends on the threshold voltage of the PMOS transistor P
1
. Accordingly, operation of the typical half power supply voltage generating circuit is disabled when the supply voltage Vcc is below a voltage value of VTP+VTN.
For example, assuming that the supply voltage Vcc is 1.5 V, the output voltage VOUT is 0.75 V. Assume threshold voltage of the PMOS transistor P
1
is 0.8 V and the threshold voltage of the NMOS transistor N
2
is 0.75 V. When the output voltage VOUT transits to 0.65 V from 0.75 V, a voltage between the source and the gate of the PMOS transistor P
1
becomes 0.85 V and a voltage between the source and the gate of the NMOS transistor N
2
becomes 0.65 V. Therefore, the NMOS transistor N
2
is turned off, disabling the circuit.
Likewise, when the output voltage VOUT transits to 0.85 V from 0.75 V, a voltage difference between the source and the gate of the PMOS transistor P
1
becomes 0.65 V and a voltage difference between the source and the gate of the NMOS transistor N
2
becomes 0.85 V. Therefore, the PMOS transistor P
1
is turned off, disabling the circuit.
In the half power supply voltage generating circuit of
FIG. 1
, when the supply voltage Vcc is below 1.55 V (VTP+VTN), the output voltage VOUT becomes below 0.8 V, which is lower than a threshold voltage of the PMOS transistor P
1
and/or a threshold voltage of the NMOS transistor N
2
. The PMOS transistor P
1
and/or the NMOS transistor N
2
are turned off and the circuit disabled.
A disadvantage of the half power supply voltage generating circuit of
FIG. 1
is that it is inoperable when the output voltage of the half power supply voltage generating circuit is lower than a threshold voltage of the PMOS or NMOS transistors. This disadvantage is most often witnessed in advanced semiconductor memory devices where low supply voltages are common. And, the half power supply voltage generating is used to pre-charge bit-line pairs and data line pairs with half power supply voltage in semiconductor devices using relatively high supply voltages. The half power supply voltage generating circuit, however, can not be used to pre-charge bit-line and data line pairs in advanced semiconductor memory devices because the pre-charge voltage decreases to a level lower than the threshold voltage of the transistors included therein.
SUMMARY OF THE INVENTION
It is an object of the present invention to overcome the disadvantages associated with prior half voltage supply generating circuits.
It is another object of the present invention to provide a half power supply voltage generator capable of operating even if the half power supply voltage is lower than a threshold voltage of a transistor included therein.
It is yet another object of the present invention to provide a semiconductor device using a half power supply voltage generator capable of operating at a relatively low supply voltage.
A power supply voltage generating circuit is adapted to generate an output voltage. In one embodiment, the power supply voltage generating circuit comprises first active resistor means connected between a supply voltage and a first node, the first active resistor means having a resistance that varies responsive to the output voltage. First passive resistor means are connected in parallel to the first active resistor means. First voltage regulating means are connected between the first node and a second node adapted to regulate a voltage at the first node responsive to a voltage at the second node. Second voltage regulating means are connected between the second node and a third node
Marger & Johnson & McCollom, P.C.
Tran M.
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