Electronic digital logic circuitry – Multifunctional or programmable – Sequential or with flip-flop
Patent
1997-10-22
1999-11-30
Santamauro, Jon
Electronic digital logic circuitry
Multifunctional or programmable
Sequential or with flip-flop
326 93, 365221, H03K 1900
Patent
active
059949201
ABSTRACT:
The invention concerns an asynchronous state machine with a programmable tSKEW which may be used to generate a half-empty and half-full flags in a synchronous FIFO buffer. The present invention may reduce the delay associated in producing the half-full or half-empty flags from a typical eight gate delays, to as little as no gate delays. The reduction may be accomplished by using a first state machine which can make an internal flag go low, or active, and a second state machine which can make the internal flag go high, or inactive. The functioning of the first and second state machines may be controlled by a blocking logic. The output of each of the state machines may be stored in a latch. The output of the latch may be presented to an input of the blocking logic, which may be used by the blocking logic to control the activity of the state machines.
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Hawkins Andrew L.
Narayana Pidugu L.
Cypress Semiconductor Corp.
Maiorana P.C. Christopher P.
Santamauro Jon
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