Guest interrupt controllers for each processor to aid...

Details Guest interrupt controllers for each processor to aid... Guest interrupt controllers for each processor to aid...

2009-11-03

2011-11-08

Rinehart, Mark (Department: 2111)

Electrical computers and digital data processing systems: input/

Interrupt processing

C710S200000, C710S240000

Reexamination Certificate

active

08055827

ABSTRACT:
In one embodiment, a system comprises a processor, a first interrupt controller coupled to the processor, and a second interrupt controller coupled to the processor. The first interrupt controller is configured to signal the processor for an interrupt in response to receiving a first interrupt message communicating a first interrupt that is targeted at a host in the system. The second interrupt controller is configured to signal the processor for an interrupt in response to receiving a second interrupt message communicating a second interrupt that is targeted at a guest that is controlled by the host and that is executable on the processor.

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