Guardwall structures for ESD protection

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257SE51005

Reexamination Certificate

active

11155062

ABSTRACT:
A semiconductor circuit for protecting an I/O pad against ESD events comprising a pMOS transistor (510) in a first n-well (511) having its source connected to Vdd and the first n-well, and its drain connected to the I/O pad; the transistor has a finger-shaped contact (513) to the first n-well, which touches source junction512c. Source512has further an ohmic (silicided) connection to contact513. A finger-shaped diode (520) with its cathode (521) is located in a second n-well and connected to the I/O pad, and its anode connected to ground. The anode is positioned between the cathode and the first n-well, whereby the finger-shaped anode and cathode are oriented approximately perpendicular to the finger-shaped transistor n-well contact. Further a third finger-shaped n-well (551) positioned between the first n-well and the diode, the third n-well connected to power (Vdd) and approximately perpendicular to the first n-well contact, acting as a guard wall (550).

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