Guardwall structures for ESD protection

Details Guardwall structures for ESD protection Guardwall structures for ESD protection

2006-12-05

2006-12-05

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S356000, C257S357000, C257S358000, C257S359000, C257S360000, C257S361000, C257S363000

Reexamination Certificate

active

07145204

ABSTRACT:
A semiconductor circuit for protecting an I/O pad against ESD events comprising a pMOS transistor (510) in a first n-well (511) having its source connected to Vdd and the first n-well, and its drain connected to the I/O pad; the transistor has a finger-shaped contact (513) to the first n-well. Further a finger-shaped diode (520) with its cathode (521) located in a second n-well and connected to the I/O pad, and its anode connected to ground. The anode is positioned between the cathode and the first n-well, whereby the finger-shaped anode and cathode are oriented approximately perpendicular to the finger-shaped transistor n-well contact. Further a third finger-shaped n-well (551) positioned between the first n-well and the diode, the third n-well connected to ground and approximately perpendicular to the first n-well contact, acting as a guard wall (550).

REFERENCES:
patent: 6646309 (2003-11-01), Chen
patent: 6690066 (2004-02-01), Lin et al.
patent: 6858902 (2005-02-01), Salling et al.
patent: 2002/0033507 (2002-03-01), Maria Verhaege et al.

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