Electrical computers and digital processing systems: support – Multiple computer communication using cryptography – Protection at a particular protocol layer
Reexamination Certificate
2000-05-02
2004-05-04
Jung, David (Department: 2134)
Electrical computers and digital processing systems: support
Multiple computer communication using cryptography
Protection at a particular protocol layer
C713S190000, C713S189000
Reexamination Certificate
active
06732276
ABSTRACT:
BACKGROUND OF THE INVENTION
Computer systems are known in which instructions include a guard indicator so that the execution or otherwise of the instruction is dependent upon the guard value. Problems do however arise when a plurality of instructions are executed simultaneously in a plurality of parallel execution units. This may arise in computer systems operating in superscalar or very long instruction word (VLIW) instruction modes so that the execution of some instructions may effect the guard values to be associated with other instructions in parallel execution units. Problems may also arise from pipelined execution of instructions so that the execution of some later instructions commences prior to the completion of execution of earlier instructions in the pipeline.
It is an object of the present invention to provide computer apparatus and methods which enable efficient transfer of guard values between more than one execution units.
Guarded instruction execution has the same meaning as predicated instruction execution.
SUMMARY OF THE INVENTION
The invention provides a computer system for executing instructions having assigned guard indicators, which system comprises instruction supply circuitry, a plurality of parallel execution units for receiving respective instructions from the supply circuitry, each instruction having a respective guard indicator selected from a set of guard indicators, common to the plurality of execution units, one of said execution units including a master guard value store containing a master representation of current values for the guard indicators in said set of guard indicators, another of said execution units including a shadow guard value store containing a secondary representation of values for the guard indicators in said set, guard ownership circuitry to indicate whether said shadow guard value store owns the current value for a guard indicator, and guard value transfer circuitry operable to transfer a guard value from said master store to said another execution unit thereby enabling selection of a guard value for said another of said execution units from either the master or shadow guard value store depending on the indication of the guard ownership.
Preferably said execution unit includes circuitry for executing guard value modifying instructions and said guard value transfer circuitry is operable to transfer to, and thereby update, said master guard value store any modified guard value generated in said another execution unit.
Preferably the instruction supply circuitry comprises a control unit common to each parallel execution unit, said control unit including said guard ownership circuitry and being operable in response to an indication of guard ownership to supply to the execution unit instructions to enable access to a selected one of the guard value stores.
Preferably said control unit includes a further secondary store of guard values and said guard ownership circuitry is operable to indicate whether ownership of a selected guard value is held by said secondary store of guard values in the control unit.
Preferably said control unit includes an instruction dispatch unit for dispatching instructions to said parallel execution units, said dispatch unit being responsive to said secondary store of guard values and to said guard ownership circuitry to prevent dispatch of instructions for which the guard value is owned by the control unit and known to be false.
Preferably said dispatch unit is operable to dispatch an instruction with a predetermined guard value requiring normal execution of the instruction in response to locating that the guard value for the instruction is owned by the control unit and indicated by said secondary store as a true value.
The invention provides a method of executing instructions in a computer system, said instructions having assigned guard indicators, which method comprises supplying a plurality of instructions to parallel execution units, each instruction having a respective guard indicator selected from a set of guard indicators common to the plurality of execution units, holding a master set of current values for the guard indicators in one execution unit, holding a shadow set of guard values in another execution unit, indicating which execution unit has guard ownership for the guard indicator of any one instruction being executed, execution of an instruction in said another execution unit obtaining the guard value from the shadow value if guard ownership of that guard indicator is owned by said another execution unit or effecting a transfer of the master guard value from said one execution unit if guard ownership of that guard value is not owned by said another execution unit.
Preferably the method includes executing instructions to modify said guard values wherein execution of an instruction to modify a guard value in said one execution unit updates said master value without changing said shadow value.
Preferably execution of an instruction in said another execution unit to modify a guard value is used to update said shadow guard value and to transfer the new guard value to update the master value in said one execution unit.
REFERENCES:
patent: 5889984 (1999-03-01), Mills
patent: 6643781 (2003-11-01), Merriam
patent: 6651171 (2003-11-01), England et al.
patent: 6658567 (2003-12-01), Barton et al.
patent: 0 403 014 (1990-12-01), None
patent: 0 490 524 (1992-06-01), None
Yoshida et al., A strategy for avoiding pipeline interlock delays in a microprocessor, Computer Design: VLSI in Computers and Processors, 1990, ICCD '90 Proceedings, 1990 IEEE International Conference on Sep. 17-19, 1990, pp. 14-19.*
Sakai et al., Reduced interprocessor-communication architecture for supporting programming models, Programming Models for Massively Parallel Computers, 1993, Proceedings, Sep. 20-23, 1993, pp. 134-143.*
Mills, A pipelined architecture for logic programming with a complex but single-cycle instruction set, Tools for Artifical Intelligence, 1989, Architecture, Languages and Algorithms, IEEE International Workshop on, Oct. 23-25, 1989, pp. 526-533.*
European Search Report from European Application No. 99410053.
Labrousse J, et al.,Create-Life: A Modular Design Approach for High Performace ASIC's, Computer Society International Conference (COMPCOM), Spring Meeting, Los Alamitos, Feb. 26-Mar. 2, 1990, pp. 427-433, XP000146217.
Cofler Andrew
Ducousso Laurent
Fel Bruno
Jorgenson Lisa K.
Jung David
Morris James H.
STMicroelectronics S.A.
Wolf Greenfield & Sacks P.C.
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