Guard wafer for semiconductor structure fabrication

Details Guard wafer for semiconductor structure fabrication Guard wafer for semiconductor structure fabrication

2008-05-13

2008-05-13

Leja, Ronald W. (Department: 2836)

Electricity: electrical systems and devices

Electric charge generating or conducting means

Use of forces of electric charge or field

C204S298110

Reexamination Certificate

active

07372689

ABSTRACT:
An apparatus (and method for operating the same) which allows tightly coupling the device wafer to the electrostatic chuck of the process chamber after the process chamber is conditioned. The method comprises (a) providing (i) a process chamber and (ii) an electrostatic chuck in the process chamber; (b) placing a guard wafer on the electrostatic chuck via a top surface of the electrostatic chuck; and (c) forming a particle restraining layer on essentially all surfaces that are exposed to the ambient inside the process chamber, wherein the particle restraining layer has a thickness in a first direction of at least 500 Å, wherein the first direction is essentially perpendicular to an interfacing surface between the particle restraining layer and an inner surface of the process chamber, and wherein the guard wafer comprises a material selected from the group consisting of a metal and a semiconductor oxide.

REFERENCES:
patent: 6014979 (2000-01-01), Van Autryve et al.
patent: 6468404 (2002-10-01), Lu et al.
patent: 6589398 (2003-07-01), Lu et al.
patent: 6756319 (2004-06-01), Kim
patent: 2002/0197144 (2002-12-01), Blank et al.

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