GTL to CMOS level signal converter, method and apparatus

Electronic digital logic circuitry – Interface – Logic level shifting

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326 98, H03K 19096

Patent

active

054061431

ABSTRACT:
A GTL signal to CMOS level signal converter has a sense amplifier to receive the GTL signal and a clock signal and generate a first signal in response thereto. A buffer has a plurality of clocked stages for receiving the clock signal and the first signal and for generating the CMOS signal. A clock generates the clock and supplies the clock signal to the sense amplifier and the buffer.

REFERENCES:
patent: 5023488 (1991-06-01), Gunning
patent: 5228106 (1993-07-01), Ang et al.
patent: 5311083 (1994-05-01), Wanlass
patent: 5323360 (1994-06-01), Pelley, III
patent: 5332934 (1994-07-01), Hashimoto et al.
patent: 5347177 (1994-09-01), Lipp

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