Electronic digital logic circuitry – Interface – Logic level shifting
Patent
1993-12-21
1995-04-11
Hudspeth, David R.
Electronic digital logic circuitry
Interface
Logic level shifting
326 98, H03K 19096
Patent
active
054061431
ABSTRACT:
A GTL signal to CMOS level signal converter has a sense amplifier to receive the GTL signal and a clock signal and generate a first signal in response thereto. A buffer has a plurality of clocked stages for receiving the clock signal and the first signal and for generating the CMOS signal. A clock generates the clock and supplies the clock signal to the sense amplifier and the buffer.
REFERENCES:
patent: 5023488 (1991-06-01), Gunning
patent: 5228106 (1993-07-01), Ang et al.
patent: 5311083 (1994-05-01), Wanlass
patent: 5323360 (1994-06-01), Pelley, III
patent: 5332934 (1994-07-01), Hashimoto et al.
patent: 5347177 (1994-09-01), Lipp
Hudspeth David R.
Vertex Semiconductor Corporation
LandOfFree
GTL to CMOS level signal converter, method and apparatus does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with GTL to CMOS level signal converter, method and apparatus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and GTL to CMOS level signal converter, method and apparatus will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1540691